CS5321 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5321 Datasheet PDF : 38 Pages
| |||
CS5320/21/22
ferred offset will be added internal to the
CS5320/21 and guarantee that any idle tones
present will lie out-of-band. The user should be
certain that when OFST is active (OFST =1) that
the offset voltage generated by the user circuitry
does not negate the offset added by the OFST pin.
2.3 Input Range and Overrange Conditions
The analog input is applied to the AIN+ and AINR
pins with the AIN- pin connected to GND. The in-
put is fully differential but for proper operation the
AIN- pin must remain at GND potential.
The analog input span is defined by the voltage ap-
plied between the VREF+ and VREF- input pins.
See the Voltage Reference section of this data sheet
for voltage reference requirements.
The modulator is a fourth order delta-sigma and is
therefore conditionally stable. The modulator may
go into an oscillatory condition if the analog input
is overranged. Input signals which exceed either
plus or minus full scale by more than 5 % can intro-
duce instability in the modulator. If an unstable
condition is detected, the modulator will be re-
duced to a first order system until loop stability is
achieved. If this occurs the MFLG pin will transi-
tion from a low to a high will result in an error bit
being set in the CS5322. The input signal must be
reduced to within the full scale range of the con-
verter for at least 32 MCLK cycles for the modula-
tor to recover from this error condition.
+5V
Analog
Supply
10 µF +
0.1 µF 2
1 Vdd1
GND1
22
0.1 µF
Vdd2
23
GND11
+4.5V
VREF
200Ω
0.1 µF
Signal
Source
402Ω
402Ω
-5V
Analog
Supply
+
10 µF
+ 68 µF
TANT.
0.1 µF
COG
0.1 µF
COG
5
VREF+
6
VREF-
10
AINR
28
OFST
27
LPWR
26
HBR
25
MSYNC
24
MFLG
20
MCLK
18
MDATA
9
AIN+
CS5320/21
8
AIN-
14 GND7
13 GND6
12 GND5
11 GND4
7 GND3
4 GND2
17
MDATA
15
GND8
16
GND9
19
GND10
0.1 µF Vss1
3
Vss2
21
0.1 µF
Control
Logic
+5 V
Digital
Supply
21
0.01 µF 20
VD+
5
MSYNC
6
MFLG
7
MCLK
10
MDATA
DGND
25
SID
24
SOD
26
SCLK
1
CS
28
R/W
22
DRDY
27
RSEL
23
ERROR
12
CSEL
Serial
Data
Interface
Test
Data
Clock
Source
CS5322
11
TDATA
3
CLKIN
2
SYNC
13
H/S
14
PWDN
15
USEOR
19
ORCAL
18
DECA
17
DECB
16
DECC
4
RESET
Hardware
Control
+5 V
Digital
Supply
VD+
DGND
8 0.01 µF 9
Unused logic
inputs must be
connected to
DGND or VD+
Figure 20. System Connection Diagram
DS454PP1
19
Share Link: 