CS5321-BL(2005) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5321-BL Datasheet PDF : 36 Pages
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CS5321/22
2. GENERAL DESCRIPTION
The CS5321 is a fourth-order CMOS monolithic
analog modulator designed specifically for very
high resolution measurement of signals between dc
and 1600 Hz. Configuring the CS5321 with the
CS5322 FIR filter results in a high resolution A/D
converter system that performs sampling and A/D
conversion with a dynamic range exceeding 120
dB.
The CS5321 uses a fourth-order oversampling ar-
chitecture to achieve high resolution A/D conver-
sion. The modulator consists of a 1-bit A/D
converter embedded in a negative feedback loop.
The modulator provides an oversampled serial bit
stream at 256 kbits per second (HBR=1) and 128
kbits per second (HBR=0) operating with a clock
rate of 1.024 MHz. Figure 18 illustrates the
CS5321 block diagram.
The CS5322 is a monolithic digital Finite Impulse
Response (FIR) filter with programmable decima-
tion. The CS5322 and CS5321 are intended to be
used together to form a unique high dynamic range
ADC chipset. The CS5322 provides the digital
anti-alias filter for the CS5321 modulator output.
The CS5322 consists of: a multi-stage FIR filter,
four registers (status, data, offset, and configura-
tion), a flexible serial input and output port, and a
2-channel input data multiplexer that selects data
from the CS5321 (MDATA) or user test data
(TDATA). The CS5322 decimates (64x to 4096x)
the output to any of seven selectable up-date peri-
ods: 16, 8, 4, 2, 1, 0.5 and 0.25 milliseconds. Data
is output from the digital filter in a 24-bit serial for-
mat. Figure 19 illustrates the CS5322 Block Dia-
gram.
AINR
AIN+
AIN-
Vdd1
Vss1
AGND
Vdd2
Vss2
Osc.
Detect
Digital
Control
DGND
LPWR
OFST
MFLG
VREF+
VREF-
Σ
A/D
D/A
Clock
Generation
HBR
MCLK
MSYNC
MDATA
MDATA
Figure 18. CS5321 Block Diagram
16
DS454F2
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