CS5322-BL(2005) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5322-BL Datasheet PDF : 36 Pages
| |||
CS5321/22
CS5322 SWITCHING CHARACTERISTICS (continued)
Parameter
MCLK Frequency
MCLK Duty Cycle
Rise Times:
Any Digital Input
Any Digital Output
Fall Times:
Any Digital Input
Any Digital Output
SYNC Setup Time to CLKIN rising
SYNC Hold Time after CLKIN rising
CLKIN edge to MCLK edge
MCLK rising to Valid MDATA
MSYNC Delay from MCLK rising
Symbol
(Note 24)
fc
(Note 25)
trise
(Note 25)
tfall
(Note 26)
tss
tsh
tmss
tmsh
tmsd
Min
0.512
40
-
-
-
-
20
20
-
-
-
Typ
1.024
-
-
50
-
50
-
-
30
50
90
Max Units
1.1 MHz
60
%
100
ns
200
ns
100
ns
200
ns
-
ns
-
ns
-
ns
-
ns
-
ns
Notes: 24. If MCLK is removed, the modulator will enter the power down mode.
25. Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.
26. Only the rising edge of MSYNC relative to MCLK is used to synchronize the device. MSYNC can return
low at any time as long as it remains high for at least one MCLK cycle.
C L K IN
t sh
t ss
SYNC
LSYNC*
MCLK
t mss
MSYNC
MDATA
t msd
t msd
t msh
VALID DATA
F IL T E R
SAMPLES
DATA
MFLG
* Internal tim ing signal generated in the C S 5322
t msh
VALID DATA
Figure 17. CS5321/CS5322 Interface Timing
14
DS454F2
Share Link: 