ACS8522AT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8522AT Datasheet PDF : 118 Pages
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ACS8522A SETS LITE
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Table 5 Available Damping Factors for different DPLL
Bandwidths, and associated Jitter Peak Values
Table 7 Telcordia GR-1244 CORE Specification
Parameter
Value
Bandwidth
Reg. 6B [2:0] Damping Gain Peak/ dB
Factor selected
Tolerance
±4.6 ppm over 20 year lifetime
0.1 Hz to 4 Hz 1, 2, 3, 4, 5 5
0.1
8 Hz
1
2.5
0.2
2, 3, 4, 5
5
0.1
Drift
(Frequency Drift
over supply
voltage range of
+2.7 V to +3.3 V)
±0.05 ppm/15 seconds @ constant temp.
±0.04 ppm/15 seconds @ constant temp.
±0.28 ppm/over temp. range 0 to +50°C
18 Hz
1
1.2
0.4
2
2.5
0.2
3, 4, 5
5
0.1
and a drift of 280 ppb over the temperature range 0 to
+50°C. Please contact Semtech for information on crystal
oscillator suppliers
35 Hz
1
1.2
0.4
Crystal Frequency Calibration
2
2.5
3
5
4, 5
10
70 Hz
1
1.2
2
2.5
3
5
4
10
5
20
0.2
0.1
0.06
0.4
0.2
0.1
0.06
0.03
Local Oscillator Clock
The Master system clock on the ACS8522A should be
provided by an external clock oscillator of frequency
12.800 MHz. The clock specification is important for
meeting the ITU/ETSI and Telcordia performance
requirements for Holdover mode. ITU and ETSI
specifications permit a combined drift characteristic, at
constant temperature, of all non-temperature-related
parameters, of up to 10 ppb per day. The same
specifications allow a drift of 1 ppm over a temperature
range of 0 to +70°C.
The absolute crystal frequency accuracy is less important
than the stability since any frequency offset can be
compensated by adjustment of register values in the IC.
This allows for calibration and compensation of any
crystal frequency variation away from its nominal value.
± 50 ppm adjustment would be sufficient to cope with
most crystals, in fact the range is an order of magnitude
larger due to the use of two 8-bit register locations. The
setting of the cnfg_nominal_frequency register allows for
this adjustment. An increase in the register value
increases the output frequencies by 0.0196229 ppm for
each LSB step.
Note...The default register value (in decimal) = 39321
(9999 hex) = 0 ppm offset. The minimum to maximum offset
range of the register is 0 to 65535 dec, giving an adjustment
range of -771 ppm to +514 ppm of the output frequencies, in
0.0196229 ppm steps.
Example: If the crystal was oscillating at 12.800 MHz + 5 ppm,
then the calibration value in the register to give a - 5 ppm
adjustment in output frequencies to compensate for the
crystal inaccuracy, would be:
39321 - (5 / 0.0196229) = 39066 (dec) = 989A (hex).
Output Wander
Table 6 ITU and ETSI Specification
Wander and jitter present on the output clocks are
dependent on:
Parameter
Tolerance
Value
±4.6 ppm over 20 year lifetime
z The magnitudes of wander and jitter on the selected
input reference clock (in Locked mode)
Drift
(Frequency Drift
over supply
voltage range of
+2.7 V to +3.3 V)
±0.05 ppm/15 seconds @ constant temp.
±0.01 ppm/day @ constant temp.
±1 ppm over temp. range 0 to +70°C
z The internal wander and jitter transfer characteristic
(in Locked mode)
z The jitter on the local oscillator clock
z The wander on the local oscillator clock (in Holdover
mode).
Telcordia specifications are somewhat tighter, requiring a Wander and jitter are treated in different ways to reflect
non-temperature-related drift of less than 40 ppb per day their differing impacts on network design. Jitter is always
Revision 1.00/September 2007 © Semtech Corp.
Page 20
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