SST55LD019C-45-C-MVWE View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
MFG CO.
SST55LD019C-45-C-MVWE Datasheet PDF : 79 Pages
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ATA Flash Disk Controller
SST55LD019A / SST55LD019B / SST55LD019C
Data Sheet
11.1.2.9 Status & Alternate Status Registers (Read Only)
These registers return the ATA Flash Disk Controller status when read by the host. Reading the Status register does
clear a pending interrupt while reading the alternate Status register does not. The meaning of the status bits are
described as follows:
D7
BUSY
Symbol
BUSY
RDY
DWF
DSC
DRQ
CORR
ERR
D6
D5
D4
D3
D2
D1
RDY
DWF
DSC
DRQ CORR
0
D0
ERR
Reset Value
1000 0000b
Function
The busy bit is set when the ATA Flash Disk Controller has access to the command
buffer and registers and the host is locked out from accessing the Command register and
buffer. No other bits in this register are valid when this bit is set to a 1.
RDY indicates whether the device is capable of performing ATA Flash Disk Controller
operations. This bit is cleared at power up and remains cleared until the ATA Flash Disk
Controller is ready to accept a command.
This bit, if set, indicates a write fault has occurred.
This bit is set when the ATA Flash Disk Controller is ready.
The Data-Request bit is set when the ATA Flash Disk Controller requires that information
be transferred either to or from the host through the Data register.
This bit is set when a correctable data error has been encountered and the data has
been corrected. This condition does not terminate a multi-sector Read operation.
This bit is set when the previous command has ended in some type of error. The bits in
the Error register contain additional information describing the error. It is required that
the host retry any media access command (such as Read-Sectors and Write-Sectors)
that end with an error condition.
11.1.2.10 Device Control Register (Write Only)
This register is used to control the ATA Flash Disk Controller interrupt request and to issue a software reset. This
register can be written to even if the device is busy. The bits are defined as follows:
D7
X
Symbol
SW Rst
-IEn
D6
D5
D4
D3
D2
D1
D0
Reset Value
X
X
X
1
SW Rst -IEn
0
0000 1000b
Function
This bit is set to 1 in order to force the ATA Flash Disk Controller to perform a software
Reset operation. The chip remains in reset until this bit is reset to ‘0.’
0: The Interrupt Enable bit enables interrupts
1: Interrupts from the ATA Flash Disk Controller are disabled
This bit is set to 0 at Power-on and Reset.
©2006 Silicon Storage Technology, Inc.
22
S71241-04-000
12/06
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