
LT3669/LT3669-2
TIMING DIAGRAMS
VDD
RXD1
RPU
CQ1
CQ1
CQ1
RXD1
8V
tPLHR
13V
tPHLR
tSKEWR = tPHLR – tPLHR
Figure 4. Receiver Propagation Delays
VL+
0V
VDD
0V
36692 F04
SHORT GLITCH < TBIT /16
REJECTED
CQ1
RXD1
TBIT
> TBIT /16
LONG GLITCH
DETECTED
VL+
VVTTHHHL
0V
VDD
0V
TBIT
36692 F05
Figure 5. Receiver Detection and Noise Filter
POR
CONTROL
VDD
RST
RPU
VOUT
(VLDO)
RST
VRSTTH
tUV
tRST
Figure 6. Power-On Reset Waveforms
18
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VDD / 2
36692 F06
VDD
0V
3669fa