Z8 Encore! XP® F082A Series
Product Specification
63
Table 39. IRQ0 Enable High Bit Register (IRQ0ENH)
Bit
Field
RESET
R/W
Address
7
Reserved
0
R/W
6
T1ENH
0
R/W
5
T0ENH
0
R/W
4
3
U0RENH U0TENH
0
0
R/W
R/W
FC1H
2
Reserved
0
R/W
1
Reserved
0
R/W
0
ADCENH
0
R/W
Bit
Description
[7]
Reserved
This bit is reserved and must be programmed to 0.
[6]
Timer 1 Interrupt Request Enable High Bit
T1ENH
[5]
Timer 0 Interrupt Request Enable High Bit
T0ENH
[4]
UART 0 Receive Interrupt Request Enable High Bit
U0RENH
[3]
UART 0 Transmit Interrupt Request Enable High Bit
U0TENH
[2:1]
Reserved
These bits are reserved and must be programmed to 00.
[0]
ADC Interrupt Request Enable High Bit
ADCENH
Table 40. IRQ0 Enable Low Bit Register (IRQ0ENL)
Bit
Field
RESET
R/W
Address
7
Reserved
0
R
6
T1ENL
0
R/W
5
T0ENL
0
R/W
4
3
U0RENL U0TENL
0
0
R/W
R/W
FC2H
2
1
Reserved Reserved
0
0
R
R
0
ADCENL
0
R/W
Bit
[7]
[6]
T1ENL
[5]
T0ENL
Description
Reserved
This bit is reserved and must be programmed to 0.
Timer 1 Interrupt Request Enable Low Bit
Timer 0 Interrupt Request Enable Low Bit
PS022827-1212
PRELIMINARY
Interrupt Control Register Definitions