M95512-RMN6TP View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

M95512-RMN6TP

512 Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

Instructions

M95512-W, M95512-R

6.8

Write Identification Page (available only in M95512-DR

devices)

The Identification Page (128 bytes) is an additional page which can be written and (later)

permanently locked in Read-only mode. Writing this page is achieved with the Write

Identification Page instruction (see Table 4), the Chip Select signal (S) is first driven low. The

bits of the instruction byte, address byte, and at least one data byte are then shifted in on

Serial Data input (D). Address bit A10 must be 0, address bits [A15:A11] and [A9:A7] are

Don't Care, the [A6:A0] address bits define the byte address inside the identification page.

The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input

data. The self-timed write cycle triggered by the rising edge of Chip Select (S) continues for

a period tW (as specified in Table 17 and Table 18), at the end of which the Write in Progress

(WIP) bit is reset to 0.

In the case of Figure 16, Chip Select (S) is driven high after the eighth bit of the data byte

has been latched in, indicating that the instruction is being used to write a single byte.

However, if Chip Select (S) continues to be driven low, as shown in Figure 16, the next byte

of input data is shifted in, so that more than a single byte, starting from the given address

towards the end of the same page, can be written in a single internal write cycle. Each time

a new data byte is shifted in, the least significant bits of the internal address counter are

incremented. If the number of data bytes sent to the device exceeds the page boundary, the

internal address counter rolls over to the beginning of the page, and the previous data there

are overwritten with the incoming data. (The page size of these devices is 128 bytes).

The instruction is not accepted, and is not executed, under the following conditions:

● if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a

Write Enable instruction)

● if Status register bits (BP1, BP0) = (1, 1)

● if a write cycle is already in progress

● if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the eighth bit, b0, of the last data byte that was latched in)

● if the Identification page is locked by the Lock Status bit

Figure 16. Write Identification Page sequence

3

                      

#

)NSTRUCTION

BITADDRESS

$ATABYTE

$

  



(IGHIMPEDANCE

1

!I

26/48

Doc ID 11124 Rev 13

Share Link: