CLC1002ISO8X View Datasheet(PDF) - Cadeka Microcircuits LLC.
Part Name
Description
MFG CO.
CLC1002ISO8X Datasheet PDF : 17 Pages
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Data Sheet
Driving Capacitive Loads
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
RS, between the amplifier and the load to help improve
stability and settling performance. Refer to Figure 5.
Input
+
-
Rf
Rg
Rs
Output
CL
RL
3
6
G=5
2
4
1
Output
2
0
0
Input
-1
-2
-2
-4
-3
0
-6
50 100 150 200 250 300 350 400 450
Time (us)
Figure 5. Addition of RS for Driving
Capacitive Loads
Table 1 provides the recommended RS for various capaci-
tive loads. The recommended RS values result in <=1dB
peaking in the frequency response. The Frequency Re-
sponse vs. CL plots, on page 7, illustrates the response of
the CLC1002.
CL (pF)
10
22
47
100
470
RS (Ω)
43
30
20
12
4.3
-3dB BW (MHz)
275
235
190
146
72
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of ad-
ditional overshoot and ringing.
Overdrive Recovery
Figure 6. Overdrive Recovery
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified volt-
age range. Overdrive recovery is the time needed for the
amplifier to return to its normal or linear operating point.
The recovery time varies, based on whether the input or
output is overdriven and by how much the range is ex-
ceeded. The CLC1002 will typically recover in less than
25ns from an overdrive condition. Figure 6 shows the
CLC1002 in an overdriven condition.
Evaluation Board #
Products
CEB002
CLC1002 in SOT23-5
CEB003
CLC1002 in SOIC-8
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com 15
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