CS48LV13-ENZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS48LV13-ENZR Datasheet PDF : 26 Pages
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5 Pin Descriptions
Pin Name
DAO_D1
DAI_D2
DAO_D2
DAI_D1
SCLK
LRCLK
CLOCK
MCLK
MISO/SDA
MOSI
CLK/SCL
CS
DBDA
DBCK
RESET
INT
BUSY/
I2C_SELECT
VD
VPLL
VL
GND
Thermal Pad
CSP
Ball #
A1
QFN
Pin #
19
B3
20
B4
21
A2
22
A4
24
A3
23
A5
1
B2
18
D3
8
D2
9
D4
6
C4
7
B1
17
C1
13
D1
12
C2
11
C3
10
B5
4,16
—
2
D5/
5,14
C5
3,15
—
Pin Functions
Digital Audio Data Output 1 (Host/Tx/Uplink)
• (O) DAO output 1 for two’s complement serial audio data
Digital Audio Input 2 (Mic In)
• (I) Two’s complement serial audio data input 2 (DAI_D2)
Digital Audio Data Output 2 (Receiver/Speakers)
• (O) Two’s complement serial audio data output 2
Digital Audio Data Input 1 (Host/Rx/Downlink)
• (I) DAI Input 1 for two’s complement serial audio data
Digital Audio Clock
• DAI serial audio bit clock
Digital Audio Clock
• (I/O) DAI Left/Right Clock (Frame Sync)
Reference Clock Input
• (I) Reference clock for internal PLL
Master Audio Clock
• (I/O) High-speed serial audio clock (no connect for most applications)
Serial Control Data
• (O) Serial data output for SPI slave mode
• (Open-Drain Bidir) Data for I²C serial control
Serial Control Data
• (I) Serial data input for SPI slave mode
Serial Control Port Clock
• (I) Serial control clock for SPI slave mode
• (Open-Drain Bidir.)Serial control clock for I²C slave
Serial Control Port Select
• (I) Chip select for SPI slave mode
Debug Serial Control Data
• (Open-Drain Bidir) Open-drain serial data for the I²C debug serial control port
Debug Serial Control Port Clock
• (Open-Drain Bidir.) Open-drain serial clock for the I²C debug serial control port
Reset
• (I) Active low. Registers are reset to default settings and boot mode selected
Interrupt (requires 10 K external pull-up resistor)
• (Open-Drain Output) Active low. Programmable interrupt output
Busy Indicator
• (Open-Drain Output) Active low. DSP busy signal output
• (I) Boot mode select 0 on rising edge of RESET (selects boot from I2C rather than the default SPI)
Digital Core and Memory Power
• (I) Power supply for the core and memory section
PLL Power
• (I) QFN package only. Power supply for PLL—tie to VD.
Digital Interface Power
• (I) Sets voltage reference level for serial audio interfaces and SP
Ground
• (I) Ground reference
Thermal Pad (QFN package only)
• (I) Thermal relief pad for optimized heat dissipation. This pad must be connected to GND.
DS1057F1
22
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