Z80230 View Datasheet(PDF) - Zilog

Part Name

Description

MFG CO.

Z80230

Zilog SCC Serial Communication Controller

Zilog 

SCC™/ESCC™ User’s Manual

Interfacing the SCC/ESCC

2.4 INTERFACE PROGRAMMING (Continued)

Start

No

Interrupt

Condition

Exits?

Yes

No

Specific

Interrupt Enable

(IEx=1)?

Yes

Interrupt Pendi

Set (IP=1)

No

Master

Interrupt Enable

(MIE=1)?

Yes

No

Is Peripheral

Enable Pin Act

(IEI=H)?

Yes

Peripheral Request

Interrupt (INT=L)

CPU Initiates Statu

Decode (INTACK=L

IEI/IEO Daisy Chain

Settles (Wait for DS

Unit Selected for CPU No

Service (IUS=1)

No

Service

Routine Comple

?

Yes

(Option) Check Othe

Internal IP, Bits,

RESET IUS and Ex

Has Higher

Priority Periphera

Disabled Unit?

(IEI=L)

Yes

CPU Services Highe

Priority Periphera

Priority

Service

Complete?

Yes

Interrupt Still

Pending (IP=1)

?

No

No

Yes

Figure 2-13. Interrupt Flow Chart (for each interrupt source).

2-20

UM010901-0601

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