Z80230 View Datasheet(PDF) - Zilog

Part Name

Description

MFG CO.

Z80230

Zilog SCC Serial Communication Controller

Zilog 

SCC™/ESCC™ User’s Manual

Interfacing the SCC/ESCC

2.2 Z80X30 INTERFACE TIMING (Continued)

2.2.3 Z80X30 Interrupt Acknowledge Cycle Timing

The interrupt acknowledge cycle timing for the Z80X30 is

shown in Figure 2-3. The address on AD7-AD0 and the

state of /CS0 and /INTACK are latched by the rising edge

of /AS. However, if /INTACK is Low, the address, /CS0,

CS1 and R//W are ignored for the duration of the interrupt

acknowledge cycle.

/AS

/CS0

AD7 - AD0

/DS

/INTACK

IEI

IEO

/INT

Vector

Figure 2-3. Z80X30 Interrupt Acknowledge Cycle

2-4

UM010901-0601

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