Z80230 View Datasheet(PDF) - Zilog

Part Name

Description

MFG CO.

Z80230

Zilog SCC Serial Communication Controller

Zilog 

Application Note

The Zilog Datacom Family with the 80186 CPU

SERIAL INTERFACING (Continued)

With jumpers installed to make DCD and CTS unbalanced,

J4 can also be used for an additional RS-232 serial link.

Connect a “Mac to Hayes modem” cable to J4, and

optionally a null modem interconnect module to the other

end. The cable internally grounds the RxD+ and TxD+

leads so that RxD– and TxD– act like RS-232 signals.

Macintosh systems also include provisions for

synchronous clock inputs. It is not known whether these

features are used by any applications, or attached

hardware. On all known Macs, the SCC’s TRxC pin is

driven from the same signal as CTS; to be compatible with

this feature, connect J15-J4 to pins 4 and 9 of the selected

connector among J5-J10.

On the Mac SE, Mac II, and later models, a multiplexing

scheme is provided on SCC channel A’s RTxC pin to drive

from either the same signal as DCD, or from an on-board

3.672 MHz clock. (Channel B always had the 3.672 MHz

clock.) The former capability can be provided by

connecting J15-J6 to pins 6 and 8 of the selected

connector among J5-J10. The latter capability can be only

approximated using the 80186 clock with different baud

rate divisors, or by using another oscillator. (The board

includes an unpopulated 4-pin oscillator socket that might

be useful in this regard.)

6-72

UM010901-0601

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