CS5516-ASZ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5516-ASZ

16/20-bit bridge transducer A/D conveter

Cirrus Logic 

CDB5516/CDB5520

Register

Conversion Data Register

Configuration Register

DAC Register

Gain Register

AIN Ratiometric Offset Register

AIN Nonratiometric Offset Register

VREF Nonratiometric Offset Register

Read

50(H)

51(H)

53(H)

52(H)

54(H)

55(H)

56(H)

Table 1. Microcontroller commands via RS-232

Write

D1(H)

D3(H)

D2(H)

D4(H)

D5(H)

D6(H)

posed of one byte for command which is trans-

mitted with its LSB first. The command is

followed by three data bytes which make up the

24-bit word to be written to the selected register

of the A/D converter. The three bytes are trans-

mitted lowest order byte first (bits 7 - 0) with the

LSB of the byte transmitted first.

Figure 3 illustrates the power supply connections

to the evaluation board. Voltages of +5 and -5

analog and +5 digital are required.

Using the Evaluation Board

Prior to using the board to evaluate the CS5516

or CS5520 A/D converter, a good understanding

of the full potential of the converter is necessary.

It is recommended that the CS5516/CS5520 de-

vice data sheet be thoroughly read prior to

attempting to use the evaluation board.

The CS5516 or CS5520 bridge transducer A/D

converter actually contains two A/D converters.

+5V

+5VA

Z1

AGND

+

C3

47µF

C4

0.1µF

One of the converters is used to convert the

VREF voltage input, and the other is used to

convert the AIN signal input. Both converters

utilize an on-chip voltage reference to perform

conversions of their respective inputs. Since

both converters use the same reference they

track one another. The digital processing logic

of the A/D converter depends on the presence of

both signals to properly compute a digital output

word. If the evaluation board is configured for

bridge measurement, and no bridge (load cell or

simulator) is connected to the bridge transducer

terminal block, the converter will output a code

of zero because no reference voltage is present

between the VREF+ and VREF- pins.

The span of the AIN input signal is determined

by a combination of the instrumentation ampli-

fier gain (X25), the programmable gain amplifier

(PGA) gain, the magnitude of the voltage be-

tween the VREF+ and VREF- input pins, and

the calibration words for gain and offset. For ex-

+5

+5VD

Z3

DGND

+

C5

47µF

C6

0.1µF

+

Z2

C1

C2

47µF

0.1µF

-5V

-5VA

Figure 3. Power Supplies

3344

DS74DB43

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