PSD913G3V-C-70MI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD913G3V-C-70MI Datasheet PDF : 94 Pages
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Preliminary Information
PSD9XX Family
The
PSD9XX
Functional
Blocks
(cont.)
Table 31. Power Management Mode Registers (PMMR0, PMMR2)**
PMMR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
*
*
*
PLD
PLD
*
APD
Array clk Turbo
Enable
1 = off 1 = off
1 = on
***Bits 0, 2, 6, and 7 are not used, and should be set to 0, bit 5 should be set to 1.
***The PMMR0, and PMMR2 register bits are cleared to zero following power up.
***Subsequent reset pulses will not clear the registers.
Bit 0
*
Bit 1 0 = Automatic Power Down (APD) is disabled.
1 = Automatic Power Down (APD) is enabled.
Bit 3 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
Bit 4 0 = CLKIN input to the PLD AND array is connected.
Every CLKIN change will power up the PLD when Turbo bit is off.
1 = CLKIN input to PLD AND array is disconnected, saving power.
PMMR2
Bit 7
*
Bit 6
PLD
array
DBE
1 = off
Bit 5
PLD
array
ALE
1 = off
Bit 4
PLD**
array
CNTL2
1 = off
Bit 3
PLD**
array
CNTL1
1 = off
Bit 2
PLD**
array
CNTL0
1 = off
Bit 1
*
**Unused bits should be set to 0.
**Refer to Table 17 the signals that are blocked on pins CNTL0-2.
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
1 = Cntl0 input to PLD AND array is disconnected, saving power.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
1 = Cntl1 input to PLD AND array is disconnected, saving power.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
1 = Cntl2 input to PLD AND array is disconnected, saving power.
Bit 5 0 = ALE input to the PLD AND array is connected.
1 = ALE input to PLD AND array is disconnected, saving power.
Bit 6 0 = DBE input to the PLD AND array is connected.
1 = DBE input to PLD AND array is disconnected, saving power.
Bit 0
*
57
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