M48Z2M1
M48Z2M1Y
16 Mbit (2Mb x 8) ZEROPOWER® SRAM
FEATURES SUMMARY
s INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, and
BATTERIES
s CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s 10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
s AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z2M1: 4.5V ≤ VPFD ≤ 4.75V
– M48Z2M1Y: 4.2V ≤ VPFD ≤ 4.5V
s BATTERIES ARE INTERNALLY ISOLATED
UNTIL POWER IS APPLIED
s PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 2Mb x 8 SRAMs
Figure 1. Packages
36
1
PLDIP36 (PL)
Module
May 2002
1/17