M25P05-VMN6T View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

M25P05-VMN6T

512 Kbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface

STMicroelectronics 

M25P05

POWER-UP, POWER-DOWN AND DELIVERY STATE

Moreover, the device ignores all Page Program

Power-up

(PP), Sector Erase (SE), Bulk Erase (BE) and

At Power-up, the device must not be selected (that

is Chip Select (S) must follow the voltage supplied

on VCC) until the supply voltage reaches

VCC(min), and a further tVSL delay has elapsed.

To avoid data corruption and inadvertent write

operations during power up, a Power On Reset

(POR) circuit is included. The logic inside the

device is held reset while VCC is less than the POR

threshold value, VWI – all operations are disabled,

and the device will not respond to any instruction.

Similarly, when VCC drops from the operating

voltage, to below the POR threshold value, VWI, all

operations are disabled and the device will not

Write Status Register (WRSR) instructions until a

time delay of tPUW has elapsed after the moment

that VCC rises above the VWI threshold. However,

the correct operation of the device is not

guaranteed if, by this time, VCC is still below

VCC(min). No Write Status Register, Program or

Erase instructions should be sent until the later of:

– tPUW after VCC passed the VWI threshold

– tVSL afterVCC passed the VCC(min) level

These values are specified in Table 7.

At Power-up, the device is in the following state:

respond to any instruction.

– The device is in the Standby mode (not the

No instructions (including Read, Write Status

Deep Power-down mode).

Register, Program or Erase instructions) should

be sent to the device until a time delay of tVSL after

VCC has risen above the VCC(min) level.

– The Write Enable Latch (WEL) bit is reset.

Figure 19. Power-up Timing

VCC

Program, Erase and Write Commands are Rejected by the Device

Chip Selection Not Allowed

VCC(min)

Reset State

of the

Device

VWI

tVSL Read Access allowed Device fully

accessible

tPUW

Table 7. Power-Up Timing and VWI Threshold

Symbol

Parameter

tVSL1 VCC(min) to S low

tPUW1 Time delay to Write instruction

VWI1 Write Inhibit Voltage

Note: 1. These parameters are characterized only.

time AI04009B

Min.

10

1.5

Max. Unit

µs

15

ms

2.5

V

21/32

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