LH28F160S5R-L70 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
LH28F160S5R-L70
Sharp Electronics
LH28F160S5R-L70 Datasheet PDF : 55 Pages
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LH28F160S5-L/S5H-L
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (NOTE 1)
[LH28F160S5-L]
• VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70°C
VERSIONS
VCC±0.25 V
(NOTE 5)
LH28F160S5-L70
VCC±0.5 V
(NOTE 6)
(NOTE 6)
UNIT
LH28F160S5-L70 LH28F160S5-L10
SYMBOL
PARAMETER
tAVAV Write Cycle Time
tPHEL
RP# High Recovery to CE#
Going Low
tWLEL WE# Setup to CE# Going Low
tELEH CE# Pulse Width
tSHEH WP# VIH Setup to CE# Going High
tVPEH VPP Setup to CE# Going High
tAVEH Address Setup to CE# Going High
tDVEH Data Setup to CE# Going High
tEHDX Data Hold from CE# High
tEHAX Address Hold from CE# High
tEHWH WE# Hold from CE# High
tEHEL CE# Pulse Width High
tEHRL CE# High to STS Going Low
tEHGL Write Recovery before Read
tQVVL
VPP Hold from Valid SRD,
STS High Z
tQVSL
WP# VIH Hold from Valid SRD,
STS High Z
NOTE
2
2
2
3
3
2, 4
2, 4
MIN.
70
1
0
50
100
100
40
40
5
5
0
25
0
0
0
MAX.
90
MIN.
80
1
0
50
100
100
40
40
5
5
0
25
0
0
0
MAX.
90
MIN.
100
1
0
50
100
100
40
40
5
5
0
25
0
0
0
MAX.
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
90 ns
ns
ns
ns
NOTES :
1. In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold
and inactive WE# times should be measured relative to
the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN and DIN for block erase,
full chip erase, (multi) word/byte write or block lock-bit
configuration.
4. VPP should be held at VPPH1 until determination of block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration success (SR.1/3/4/5 = 0).
5. See Fig. 12 "Transient Input/Output Reference
Waveform" and Fig. 14 "Transient Equivalent Testing
Load Circuit" (High Speed Configuration) for testing
characteristics.
6. See Fig. 13 "Transient Input/Output Reference
Waveform" and Fig. 14 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing
characteristics.
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