LPC47B34X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47B34X

128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications

SMSC -> Microchip 

Normal Floppy Mode

Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are ‘0’.

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

REG 3F3

0

0

0

0

0

0

tape sel1 tape sel0

Enhanced Floppy Mode 2 (OS2)

Register 3F3 for Enhanced Floppy Mode 2 operation.

DB7

DB6

REG 3F3 Reserved Reserved

DB5

DB4

Drive Type ID

DB3

DB2

DB1

DB0

Floppy Boot Drive tape sel1 tape sel0

Table 5 – Drive Type ID

DIGITAL OUTPUT REGISTER

REGISTER 3F3 - DRIVE TYPE ID

Bit 1

Bit 0

Bit 5

Bit 4

0

0

L0-CRF2 - B1

L0-CRF2 - B0

0

1

L0-CRF2 - B3

L0-CRF2 - B2

1

0

L0-CRF2 - B5

L0-CRF2 - B4

1

1

L0-CRF2 - B7

L0-CRF2 - B6

Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.

Data Rate Select Register (DSR)

Address 3F4 WRITE ONLY

This register is write only. It is used to program the data rate, amount of write precompensation,

power down status, and software reset. The data rate is programmed using the Configuration Control

Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 applications. Other applications can set

the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the

DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H,

which corresponds to the default precompensation setting and 250 Kbps.

7

6

5

4

3

2

1

0

S/W POWER 0

PRE- PRE- PRE- DRATE DRATE

RESET DOWN

COMP2 COMP1 COMP0 SEL1 SEL0

RESET 0

0

0

0

0

0

1

0

COND.

31

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