Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 29. Synchronous multiplexed PSRAM write timings
tw(CLK)
FSMC_CLK
tw(CLK)
BUSTURN = 0
FSMC_NEx
td(CLKL-NADVL)
FSMC_NADV
FSMC_A[25:16]
FSMC_NWE
td(CLKL-ADV)
FSMC_AD[15:0]
Data latency = 1
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-NADVH)
td(CLKL-AV)
td(CLKL-NWEL)
td(CLKH-AIV)
td(CLKH-NWEH)
td(CLKL-ADIV)
td(CLKL-Data)
td(CLKL-Data)
AD[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
FSMC_NBL
th(CLKH-NWAITV)
td(CLKL-NBLH)
ai14992d
68/123
Doc ID 14611 Rev 7