LTC2621C(V2) View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC2621C Datasheet PDF : 16 Pages
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LTC2601/LTC2611/LTC2621
ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), VOUT unloaded,
unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
LTC2621
LTC2611
LTC2601
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
AC Performance
tS
Settling Time (Note 6)
±0.024% (±1LSB at 12 Bits)
7
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7
7
µs
9
9
µs
10
µs
Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits)
2.7
2.7
2.7
µs
(Note 7)
±0.006% (±1LSB at 14 Bits)
4.8
4.8
µs
±0.0015% (±1LSB at 16 Bits)
5.2
µs
Voltage Output Slew Rate
0.80
0.80
0.80
V/µs
Capacitive Load Driving
1000
1000
1000
pF
Glitch Impulse
At Midscale Transition
12
12
12
nV • s
Multiplying Bandwidth
180
180
180
kHz
en
Output Voltage Noise Density At f = 1kHz
At f = 10kHz
120
120
120
nV/√Hz
100
100
100
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
µVP-P
WU
TI I G CHARACTERISTICS The q denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Note 4)
SYMBOL PARAMETER
CONDITIONS
LTC2601/LTC2611/LTC2621
MIN
TYP
MAX UNITS
VCC = 2.5V to 5.5V
t1
SDI Valid to SCK Setup
t2
SDI Valid to SCK Hold
t3
SCK High Time
t4
SCK Low Time
t5
CS/LD Pulse Width
t6
LSB SCK High to CS/LD High
t7
CS/LD Low to SCK High
t8
SDO Propagation Delay from SCK Falling Edge
t9
CLR Pulse Width
t10
CS/LD High to SCK Positive Edge
t12
LDAC Pulse Width
t13
CS/LD High to LDAC High or Low Transition
SCK Frequency
CLOAD = 10pF
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
50% Duty Cycle
q4
q4
q9
q9
q 10
q7
q7
q
q
q 20
q7
q 15
q 200
q
ns
ns
ns
ns
ns
ns
ns
20
ns
45
ns
ns
ns
ns
ns
50
MHz
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defined from code 256 to code 65,535.
Note 3: Digital inputs at 0V or VCC.
Note 4: Guaranteed by design and not production tested.
Note 5: Inferred from measurement at code KL = 0.016(2N/VREF) and at
full scale.
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
2601f
4
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