CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Write

Read

bits[7:4, 2] ignored

bit[3] enable

0

state machine cleared

1

state machine enabled

bit[1] force KBDATA/MSDATA pin low

0

do not force low

1

force low

bit[0] force KBCLK/MSCLK pin low

0

do not force low

1

force low

bit[7] TXE, shift register empty

0

not ready

1

enabled and ready to transmit

bit[6] TXB, transmitter busy

0

not busy

1

currently sending data

bit[5] RXF, receive shift register full

0

not full

1

ready to read

bit[4] RXB, receiver busy

0

not busy

1

currently receiving data

bit[3] ENA, state machine enable

0

disabled

1

enabled

bit[2] RXP, receive parity bit, odd parity bit for last received data

bit[1] KBDATA/MSDATA pin value after synchronization

bit[0] KBCLK/MSCLK pin value after synchronization

There is also a data register (KBDAT) used for write bytes to be transmitted across the serial link and to

read bytes received. The KBDAT register is programmed at address 0x03200004, and the MSEDAT

(Mouse Data register) is programmed at address 0x032000A8.

The interfaces generate two interrupts each, one to indicate that the transmit buffer is empty and thus that

another byte can be transmitted, and one to indicate that a byte has been received by the interface. These

interrupt bits are processed by the IRQB register set (for keyboard) and the IRQD register set (for mouse).

The keyboard interface is held in reset until the enable bit in the control register is set. The interface can

be controlled on the basis of the interrupts generated, or by polling the status flags in the control register.

The Tx interrupt is generated when the transmit buffer has been emptied and the interface is ready to be

programmed with another character for transmission. The Rx interrupt is set when a complete character

has been received in the receive buffer, and the byte is ready to be read from the register. The received

data parity bit, RXP, is available in the control register at bit 2. Odd parity is used. The keyboard and

mouse interface state machines are clocked by the 8-MHz I/O system clock.

The KCLK/MSCLK signal is always driven by the keyboard/mouse, unless CL-PS7500FE wishes to pre-

vent the peripheral from transmitting (because it is about to transmit some data itself). When data is

June 1997

ADVANCE DATA BOOK v2.0

I/O SUBSYSTEMS

115

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