STPCI2HEYC(2002) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STPCI2HEYC
(Rev.:2002)

X86 Core PC Compatible System-on-Chip for Terminals

STMicroelectronics 

DESIGN GUIDELINES

In the case of higher clock load it is recommended

to use a zero-delay clock buffer as described in

Figure 6-9. This approach is also recommended

when implementing the delay on PCICLKI

according to the PCI section of the Electrical

Specifications chapter.

Figure 6-9. PCI clock routing with zero-delay clock buffer

PCICLKI

PCICLKI

PCICLKO

PLL

CY2305

Device A

Device B

Device C

Device D

Implementation 1

PCICLKO

PLL

CY2305

Device A

Device B

Device C

Device D

Implementation 2

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Issue 1.0 - July 24, 2002

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