STPCI2GDYI(2002) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STPCI2GDYI Datasheet PDF : 111 Pages
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ELECTRICAL SPECIFICATIONS
4.5.3. SDRAM INTERFACE
Figure 4-5, Table 4-10, Table 4-11 lists the AC
characteristics of the SDRAM interface. The
MCLKx clocks are the input clock of the SDRAM
devices.
Figure 4-5. SDRAM Timing Diagram
MCLKx
MCLKI
STPC.output
Tdelay
Thigh
Tcycle
Tlow
Toutput (max)
Toutput (min)
STPC.input
Thold
Tsetup
Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range
Name Parameter
Min Typ
Tcycle MCLKI Cycle Time
10
Thigh MCLKI High Time
4
Tlow MCLKI Low Time
4
MCLKI Rising Time
MCLKI Falling Time
Tdelay MCLKx to MCLKI delay
2.1
MCLKI to RAS# Valid
1.6
MCLKI to CAS# Valid
1.6
MCLKI to CS# Valid
1.6
Toutput MCLKI to DQM[ ] Outputs Valid
1.35
MCLKI to MD[ ] Outputs Valid
1.35
MCLKI to MA[ ] Outputs Valid
1.6
MCLKI to MWE# Valid
1.6
Tsetup MD[63:0] setup to MCKLI
7.5
Thold MD[63:0] hold from MCKLI
-0.36
Note: These timings are for a load of 50pF, part running at 100MHz and ReadCLK not activated
Max
1
1
5.2
5.2
5.2
5.2
5.2
5.2
5.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The PC100 memory is recommended to reach
90MHz operation.
50/111
Issue 1.0 - July 24, 2002
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