Table 2-6. Pinout
Pin#
AE14
AB14
AC14
AF15
AE15
AD15
AC15
AD14
Pin Name
TFTB5
TFTLINE
TFTFRAME
TFTDE
TFTENVDD
TFTENVCC
TFTPWM
TFTDCLK
D21
OC
A20
USBDMNS[0]
A18
USBDMNS[1]
A21
USBDPLS[0]
A19
USBDPLS[1]
E20
POWERON
AC22
AC24
AD21
AE24
AC21
AD25
AD22
AC26
AD23
AA22
AE22
AC25
AB21
AD26
AE23
AB23
CTS0#
CTS1#
DCD0#
DCD1#
DSR0#
DSR1#
DTR0#
DTR1#
RI0#
RI1#
RTS0#
RTS1#
RXD0
RXD1
TXD0
TXD1
AD20
AB19
AC20
AB20
KBCLK
KBDATA
MDATA
MCLK
AA23 PE
W24
SLCT
W23
BUSY
W25
ERR#
W26
ACK#
V22
PDDIR
V24
STROBE#
V25
INIT#
V26
AUTOFD#
U22
SLCTIN#
Y22
PPD[0]
AA24 PPD[1]
AA25 PPD[2]
Note1; This signal is multiplexed
see Table 2-4
Table 2-6. Pinout
Pin#
AA26
Y24
Y25
Y26
W22
Pin Name
PPD[3]
PPD[4]
PPD[5]
PPD[6]
PPD[7]
AC19
AD19
SCL / DDC[1]
SDA / DDC[0]
C2
GPIO[0]
C1
GPIO[1]
D3
GPIO[2]
D2
GPIO[3]
D1
GPIO[4]
E4
GPIO[5]
E3
GPIO[6]
E2
GPIO[7]
E1
GPIO[8]
F5
GPIO[9]
F4
GPIO[10]
F3
GPIO[11]
F2
GPIO[12]
G5
GPIO[13]
G4
GPIO[14]
G2
GPIO[15]
H2
TCLK
J5
TRST
H5
TDI
H3
TMS
H1
TDO
G1
AD10
C25
SCAN_ENABLE
COL_SEL
SPKRD
AD16
Y23
AE20
AB26
AE19
AE18
AE21
VDD_DCLK_PLL
VDD_DEVCLK_PLL
VDD_HCLKI_PLL
VDD_HCLKO_PLL
VDD_MCLKI_PLL
VDD_MCLKO_PLL
VDD_PCICLK_PLL
F13
VDD_CORE
F15
VDD_CORE
F17
VDD_CORE
K6
VDD_CORE
M21
VDD_CORE
N6
VDD_CORE
P21
VDD_CORE
Note1; This signal is multiplexed
see Table 2-4
PIN DESCRIPTION
Table 2-6. Pinout
Pin#
R6
U21
AA10
AA12
AA14
Pin Name
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
A2
A25
B1
B26
F7
F11
F20
G6
G21
H6
J21
K21
U6
V6
Y6
Y21
AA7
AA16
AA18
AA20
AE01
AE26
AF02
AF25
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A1
GND
A26
GND
B2
GND
B25
GND
C3
GND
C24
GND
D4
GND
D10
GND
D16
GND
D23
GND
E5
GND
E22
GND
F6
GND
F8
GND
F9
GND
F10
GND
F12
GND
F14
GND
F16
GND
F18
GND
Note1; This signal is multiplexed
see Table 2-4
Issue 1.0 - July 24, 2002
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