CS5460 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5460

Single Phase Bi-Directional Power/Energy IC

Cirrus Logic 

CS5460

5. FUNCTIONAL DESCRIPTION

5.1 Interrupt and Watchdog Timer

5.1.1 Interrupt

The INT pin is used to indicate that an event has

taken place in the converter that needs attention.

These events inform the system about operation

conditions and internal error conditions. The INT

signal is created by combining the Status register

with the Mask register. Whenever a bit in the Status

register becomes active, and the corresponding bit

in the Mask register is a logic 1, the INT signal be-

comes active. The interrupt condition is cleared

when the bits of the status register are returned to

their inactive state.

5.1.1.1 Clearing the Status Register

Unlike the other registers, the bits in the Status reg-

ister can only be cleared (set to logic 0). When a

word is written to the Status register, any 1s in the

word will cause the corresponding bits in the Status

register to be cleared. The other bits of the status

register remain unchanged. This allows the clear-

ing of particular bits in the register without having

to know the state of the other bits. This mechanism

is designed to facilitate handshaking and to mini-

mize the risk of losing events that haven’t been pro-

cessed yet.

5.1.1.2 Typical use of the INT pin

The steps below show how interrupts can be han-

dled.

Initialization:

Step I0 - All Status bits are cleared by writing

FFFFFF (Hex) into the Status register.

Step I1 - The conditional bits which will be used to

generate interrupts are then written to logic 1 in the

Mask register.

Step I3 - Enable interrupts.

Interrupt Handler Routine:

Step H0 - Read the Status register.

Step H1 - Disable all interrupts.

Step H2 - Branch to the proper interrupt service

routine.

Step H3 - Clear the Status register by writing back

the value read in step H0.

Step H4 - Re-enable interrupts.

Step H5 - Return from interrupt service routine.

This handshaking procedure insures that any new

interrupts activated between steps H0 and H3 are

not lost (cleared) by step H3.

5.1.1.3 INT Active State

The behavior of the INT pin is controlled by the SI1

and SI0 bits of the configuration register. The pin

can be active low (default), active high, active on a

return to logic 0 (rising edge), or activate on a re-

turn to logic 1 (falling edge).

5.1.1.4 Exceptions

The IC (Invalid Command) bit of the Status register

can only be cleared by performing the port initial-

ization sequence. This is also the only Status regis-

ter bit that is active low.

To properly clear the WDT (WatchDog Timer) bit

of the Status register, one must first read the Energy

register, then clear the bit in the status register.

5.1.2 Watch Dog Timer

The Watch Dog Timer (WDT) is provided as

means of alerting the system that there is a potential

breakdown in communication with the micro-con-

troller. By allowing the WDT to cause an interrupt,

a controller can be brought back, from some un-

known code space, into the proper code for pro-

cessing the data created by the converter. The

time-out is preprogrammed to approximately 5 sec-

onds. The countdown restarts each time the Energy

register is read. Under typical situations, the Ener-

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DS279PP5

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