
CS61880
RCLK
RPOS/RNEG
CLKE = 1
RPOS/RNEG
CLKE = 0
tsu
th
tsu
th
Figure 20. Recovered Clock and Data Switching Characteristics
TCLK
TPOS/TNEG
tpwh2
tpw2
tsu2
th2
Figure 21. Transmit Clock and Data Switching Characteristics
tr
tf
Any Digital Output
90%
10%
90%
10%
Figure 22. Signal Rise and Fall Characteristics
DS450PP2
59