CS61880-IB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS61880-IB

Octal E1 Line Interface Unit

Cirrus Logic 

CS61880

19.7 Master Clock Switching Characteristics

Parameter

MASTER CLOCK (MCLK)

Master Clock Frequency

Master Clock Tolerance

Master Clock Duty Cycle

Symbol Min.

MCLK

-

-

-100

40

19.8 Transmit Switching Characteristics

Parameter

TCLK Frequency

TPOS/TNEG Pulse Width (RZ Mode)

TCLK Tolerance (NRZ Mode)

TCLK Duty Cycle

TCLK Pulse Width

TCLK Burst Rate

Note 10

TPOS/TNEG to TCLK Falling Setup Time (NRZ Mode)

TCLK Falling to TPOS/TNEG Hold time (NRZ Mode)

TXOE Asserted Low to TX Driver HIGH-Z

TCLK Held Low to Driver HIGH-Z

Note 20

Symbol

1/tpw2

tpwh2/tpw2

tsu2

th2

Min.

-

236

-50

-

20

-

25

25

-

8

19.9 Receive Switching Characteristics

Parameter

RCLK Duty Cycle

RCLK Pulse Width

RPOS/RNEG Pulse Width (RZ Mode)

RPOS/RNEG to RCLK rising setup time

RPOS/RNEG to RCLK hold time

RPOS/RNEG Output to RCLK Output (RZ Mode)

Rise/Fall Time, RPOS, RNEG, RCLK, LOS outputs

Note 10

Note 10

Note 10

Note 10

Note 10

Note 10

Note 19

Symbol

tsu

th

tr, tf

Notes: 19. Output load capacitance = 50pF.

20. MCLK is not active.

Min.

40

196

200

200

200

-

-

Typ Max

2.048

50

+100

60

Typ Max

2.048

-

244

252

-

50

-

90

-

-

-

20

-

-

-

-

-

1

12

20

Typ Max

50

60

244

328

244

300

244

244

-

5

-

85

Units

MHz

ppm

%

Units

MHz

nS

PPM

%

nS

MHz

nS

nS

µS

µS

Units

%

nS

nS

nS

nS

nS

nS

58

DS450PP2

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