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AM1750DPTP3 Datasheet PDF - Texas Instruments

Part NameDescriptionManufacturer
AM1750DPTP3 AM1705 ARM® Microprocessor TI
Texas Instruments TI
AM1750DPTP3 Datasheet PDF : AM1750DPTP3 pdf   
AM1705 image

The AM1705 is a low-power ARM microprocessor based on an ARM926EJ-S.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-, 16-, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core has separate 16KB of instruction and 16-KB data caches. Both memory blocks are 4-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.
The I2C, SPI, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections later in this document and the associated peripheral reference guides.
The device has a complete set of development tools for the ARM processor. These tools include C compilers and a Windows® debugger interface for visibility into source code execution.

• 375- and 456-MHz ARM926EJ-S™ RISC Core
   – 32-Bit and 16-Bit (Thumb®) Instructions
   – Single-Cycle MAC
   – ARM Jazelle® Technology
   – Embedded ICE-RT™ for Real-Time Debug
• ARM9™ Memory Architecture
   – 16KB of Instruction Cache
   – 16KB of Data Cache
   – 8KB of RAM (Vector Table)
   – 64KB of ROM
• Enhanced Direct Memory Access Controller 3
   – 2 Transfer Controllers
   – 32 Independent DMA Channels
   – 8 Quick DMA Channels
   – Programmable Transfer Burst Size
• 128KB of RAM Memory
• 3.3-V LVCMOS I/Os (Except for USB Interface)
• Two External Memory Interfaces:
   – EMIFA
   – NOR (8-Bit-Wide Data)
   – NAND (8-Bit-Wide Data)
   – EMIFB
   – 16-Bit SDRAM With 128-MB Address Space
• Three Configurable 16550-Type UART Modules:
   – UART0 With Modem Control Signals
   – 16-Byte FIFO
   – 16x or 13x Oversampling Option
   – Autoflow Control Signals (CTS, RTS) on UART0
• Two Serial Peripheral Interfaces (SPIs) Each With
   One Chip Select
• Programmable Real-Time Unit Subsystem
   – Two Independent Programmable Real-Time Unit
      (PRU) Cores
   – 32-Bit Load-Store RISC Architecture
   – 4KB of Instruction RAM per Core
   – 512 Bytes of Data RAM per Core
   – PRUSS can be Disabled Through Software to
      Save Power
   – Standard Power-Management Mechanism
   – Clock Gating
   – Entire Subsystem Under a Single PSC Clock
      Gating Domain
   – Dedicated Interrupt Controller
   – Dedicated Switched Central Resource
   – Dedicated Interrupt Controller
   – Dedicated Switched Central Resource
• Multimedia Card (MMC)/Secure Digital (SD) Card
   Interface With Secure Data I/O (SDIO)
• Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
• USB 2.0 OTG Port With Integrated PHY (USB0)
   – USB 2.0 Full-Speed Client
   – USB 2.0 Full- and Low-Speed Host
   – End Point 0 (Control)
   – End Points 1, 2, 3, and 4 (Control, Bulk,
      Interrupt, or ISOC) RX and TX
• Two Multichannel Audio Serial Ports (McASPs):
   – Six Clock Zones and 28 Serial Data Pins
   – Supports TDM, I2S, and Similar Formats
   – FIFO Buffers for Transmit and Receive (Continue...)

• Industrial Automation
• Home Automation
• Test and Measurement
• Portable Data Terminals

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