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ISPLSI2064E-200LT100 Datasheet PDF - Lattice Semiconductor

Part NameDescriptionManufacturer
ISPLSI2064E-200LT100 In-System Programmable SuperFAST™ High Density PLD Lattice
Lattice Semiconductor Lattice
ISPLSI2064E-200LT100 Datasheet PDF : ISPLSI2064E-200LT100 pdf   
ISPLSI2128E-100LT176 image

Description
The ispLSI 2064E is a High Density Programmable Logic Device. The device contains 64 Registers, 64 Universal I/O pins, four Dedicated Input Pins, three Dedicated Clock Input Pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2064E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

Features
• SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC
   — 2000 PLD Gates
   — 64 I/O Pins, Four Dedicated Inputs
   — 64 Registers
   — High Speed Global Interconnect
   — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
   — Small Logic Block Size for Random Logic
   — 100% Functionally and JEDEC Upward Compatible with ispLSI 2064 Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
   — fmax = 200 MHz Maximum Operating Frequency
   — tpd = 4.5 ns Propagation Delay
   — TTL Compatible Inputs and Outputs
   — 5V Programmable Logic Core
   — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port
   — User-Selectable 3.3V or 5V I/O Supports Mixed Voltage Systems
   — PCI Compatible Outputs
   — Open-Drain Output Option
   — Electrically Erasable and Reprogrammable
   — Non-Volatile
   — Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
   — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
   — Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
   — Complete Programmable Device Can Combine Glue Logic and Structured Designs
   — Enhanced Pin Locking Capability
   — Three Dedicated Clock Input Pins
   — Synchronous and Asynchronous Clocks
   — Programmable Output Slew Rate Control to Minimize Switching Noise
   — Flexible Pin Placement
   — Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
   — Superior Quality of Results
   — Tightly Integrated with Leading CAE Vendor Tools
   — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
   — PC and UNIX Platforms

 

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