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FIN1002M5 Datasheet PDF - Fairchild Semiconductor

Part NameDescriptionManufacturer
FIN1002M5 LVDS 1-Bit, High-Speed Differential Receiver Fairchild
Fairchild Semiconductor Fairchild
FIN1002M5 Datasheet PDF : FIN1002M5 pdf   
FIN1002 image

This single receiver is designed for high-speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high-speed transfer of clock or data. The FIN1002 can be paired with its companion driver, the FIN1001, or with any other LVDS driver.

■ Greater than 400 Mbs Data Rate
■ 3.3 V Power Supply Operation
■ 0.4 ns Maximum Pulse Skew
■ 2.5 ns Maximum Propagation Delay
■ Bus Pin ESD (HBM) Protection Exceeds 10 kV
■ Power-Off, Over-voltage tolerant Input and Output
■ Fail-safe Protection for open-circuit and non-driven,
   shorted, or terminated Conditions
■ High-impedance Output at VCC < 1.5 V
■ Meets or exceeds TIA/EIA-644 LVDS Standard
■ 5-Lead SOT23 Package saves Space

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