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Description : MACH 4 CPLD Family High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The MACH® 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation.
MACH 4 products are 5-V or 3.3-V In-System Programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
   — Excellent First-Time-FitTM and refit feature
   — SpeedLockingTM performance for guaranteed fixed timing
   — Central, input and output switch matrices
      for 100% routability and 100% pin-out retention
◆ High speed
   — 7.5ns tPD Commercial and 10ns tPD Industrial
   — 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
   — D/T registers and latches
   — Synchronous or asynchronous mode
   — Dedicated input registers
   — Programmable polarity
   — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
   — 3.3-V & 5-V JEDEC-compliant operations
   — JTAG (IEEE 1149.1) compliant for boundary scan testing
   — 3.3-V & 5-V JTAG In-System programming
   — PCI compliant (-7/-10/-12 speed grades)
   — Safe for mixed supply voltage system designs
   — Bus-FriendlyTM inputs and I/Os
   — Programmable security bit
   — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
   — Supports HDL design methodologies with results optimized for MACH 4
   — Flexibility to adapt to user requirements
   — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
   — LatticePROTM software for In-System programmability support
      on PCs and automated test equipment
   — Programming support on all major programmers including Data I/O,
      BP Microsystems, Advin, and System General

Lattice
Lattice Semiconductor
Description : ispMACH™ 4A CPLD Family High Performance E2CMOS® In-System Programmable Logic

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    — Excellent First-Time-FitTM and refit feature
    — SpeedLocking performance for guaranteed fixed timing
    — Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆  High speed
    — 5.0ns tPD Commercial and 7.5ns tPD Industrial
    — 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles

Description : XC9536 In-System Programmable CPLD

Description
The XC9572 is  a high-performance CPLD  providing advanced In-System programming and test capabilities for general purpose logic integration. It is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure2for the architecture overview.

Features
•  7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
•  72 macrocells with 1,600 usable gates
•  Up to 72 user I/O pins
•  5 V In-System Programmable (ISP)
-  Endurance of 10,000 program/erase cycles
-  Program/erase over full commercial voltage and temperature range
•  Enhanced pin-locking architecture
•  Flexible 36V18 Function Block
-  90 product terms drive any or all of 18 macrocells within Function Block
-  Global and product term clocks, output enables, set and reset signals
•  Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
•  Programmable power reduction mode in each macrocell
•  Slew rate control on individual outputs
•  User Programmable ground pin capability
•  Extended pattern security features for design protection
•  High-drive 24 mA outputs
•  3.3 V or 5 V I/O capability
•  Advanced CMOS 5V FastFLASH technology
•  Supports parallel programming of more than one XC9500 concurrently
•  Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP and 100-pin TQFP packages

ST-Microelectronics
STMicroelectronics
Description : Flash In-System-Programmable Peripherals for 16-Bit MCUs

Introduction
The PSD4000 series of Programmable Microcontroller (MCU) Peripherals brings In-System-Programmability (ISP) to Flash memory and Programmable logic. The result is a simple and flexible solution for embedded designs. PSD4000 devices combine many of the peripheral functions found in MCU based applications:
   • 4 Mbit of Flash memory
   • A secondary Flash memory for boot or data
   • Over 3,000 gates of Flash Programmable logic
   • 64 Kbit SRAM
   • Reconfigurable I/O ports
   • Programmable power management.
  
FEATURES SUMMARY
■ 5 V±10% Single Supply Voltage:
■ Up to 4 Mbit of Primary Flash Memory (8 uniform sectors)
■ 256Kbit Secondary Flash Memory (4 uniform sectors)
■ Up to 64 Kbit SRAM
■ Over 3,000 Gates of PLD: DPLD and CPLD
■ 52 Reconfigurable I/O ports
■ Enhanced JTAG Serial Port
Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 Erase/Write Cycles of PLD

Description : Programmable System Level Integration Prototyping System

Description
The Atmel ATDH40M prototyping system allows designers to quickly and economically evaluate Atmel’s family of AT40K/AT40KAL FPGA and AT94K Field Programmable System Level Integrated Circuit (FPSLIC™) devices and Atmel’s AT17 FPGA configuration memory devices. The ATDH40M board connects to any x86 PC via parallel port through a 10-pin header cable to program the AT40K/AT40KAL FPGA/AT94K FPSLIC, or through a parallel port cable to program the AT17 FPGA Configuration EEPROMs. The motherboard interfaces with various daughter boards in order to program different package footprints (see Table 1).

Features
• Hardware
   – Supports Programming for Atmel AT40K/AT40KAL and AT94KALSeries of
      SRAM-based Programmable System Level Integration (PSLI) Devices
   – Supports ISP (In-System Programming) for Atmel AT17 Series Configuration
      EEPROMs
   – Built-in Clock Source with GCLK/FCLK Jumper Settings
   – Supports Modular Docking Platform for the ATDH40D FPGA Daughter Boards
   – Runs Off Portable 9V DC Power Supply or External Power
   – Supports 5.0V or 3.3V Supply
   – Designed to Work with Atmel IDS 5.0 or Above
   – Downloading for AT40K/AT17 Devices Direct from PC Parallel Port
   – Can be Used to Support FPSLIC
• System Contents
   – ATDH2081
      25-pin Parallel to 10-pin Header Adapter
   – ATDH40Dxxx
      Package-specific Daughterboard (Variable)
   – ATDH40M
      Programming Motherboard
   – Standard Parallel Cable (PC Parallel Port DB25), 10-pin Header Cable,
      9V DC/200 mA, 2.1 mm Center Positive Power Supply

Description : 32 macrocell CPLD

DESCRIPTION
The PZ3032 CPLD (Complex Programmable Logic Device) is the first in a family of Fast Zero Power (FZP™) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZP design technique, the PZ3032 offers true pin-to-pin speeds of 8ns, while simultaneously delivering power that is less than 35µA at standby without the need for ‘turbo bits’ or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD – 70% lower at 50MHz.

FEATURES
• Industry’s first TotalCMOS™ PLD – both CMOS design and process technologies
• Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed
• High speed pin-to-pin delays of 8ns
• Ultra-low static power of less than 35µA
• Dynamic power that is 70% lower at 50MHz than competing devices
• 100% routable with 100% utilization while all pins and all macrocells are fixed
• Deterministic timing model that is extremely simple to use
• 2 clocks with Programmable polarity at every macrocell
• Support for complex asynchronous clocking
• Innovative XPLA™ architecture combines high speed with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5µ E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard and Philips CAE tools
• ReProgrammable using industry standard device programmers
• Innovative Control Term structure provides either sum terms or product terms in each logic block for:
   – Programmable 3-State buffer
   – Asynchronous macrocell register preset/reset
Programmable global 3-State pin facilitates ‘bed of nails’ testing without using logic resources
• Available in both PLCC and TQFP packages

Description : Flash In-System Programmable (ISP) peripherals for 8-bit MCUs, 3.3 V

SUMMARY DESCRIPTION
The PSD8XXFX family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and Programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications.

FEATURES SUMMARY
■ FLASH In-System Programmable (ISP) PERIPHERAL FOR 8-BIT MCUS
■ DUAL BANK FLASH MEMORIES
   – UP TO 2 Mbit OF PRIMARY FLASH MEMORY (8 Uniform Sectors, 32K x8)
   – UP TO 256 Kbit SECONDARY FLASH MEMORY (4 Uniform Sectors)
   – Concurrent operation: READ from one memory while erasing and writing the other
■ UP TO 256 Kbit of SRAM
■ 27 RECONFIGURABLE I/O PORTS
■ ENHANCED JTAG SERIAL PORT
■ PLD WITH MACROCELLS
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD - user defined internal chip select decoding
■ 27 INDIVIDUALLY CONFIGURABLE I/O PORT PINS
   The can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function I/Os.
   – 16 of the I/O ports may be configured as open-drain outputs.
In-System PROGRAMMING (ISP) WITH JTAG
   – Built-in JTAG compliant serial port allows full-chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ PAGE REGISTER
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
Programmable POWER MANAGEMENT
■ HIGH ENDURANCE:
   – 100,000 Erase/WRITE Cycles of Flash Memory
   – 1,000 Erase/WRITE Cycles of PLD
   – 15 Year Data Retention
■ 3.3V±10% SINGLE SUPPLY VOLTAGE
■ STANDBY CURRENT AS LOW AS 25µA
■ Packages are ECOPACK®

Description : Flash In-System Programmable (ISP) peripherals for 8-bit MCUs, 3.3 V

SUMMARY DESCRIPTION
The PSD8XXFX family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and Programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications.

FEATURES SUMMARY
■ FLASH In-System Programmable (ISP) PERIPHERAL FOR 8-BIT MCUS
■ DUAL BANK FLASH MEMORIES
   – UP TO 2 Mbit OF PRIMARY FLASH MEMORY (8 Uniform Sectors, 32K x8)
   – UP TO 256 Kbit SECONDARY FLASH MEMORY (4 Uniform Sectors)
   – Concurrent operation: READ from one memory while erasing and writing the other
■ UP TO 256 Kbit of SRAM
■ 27 RECONFIGURABLE I/O PORTS
■ ENHANCED JTAG SERIAL PORT
■ PLD WITH MACROCELLS
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD - user defined internal chip select decoding
■ 27 INDIVIDUALLY CONFIGURABLE I/O PORT PINS
   The can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function I/Os.
   – 16 of the I/O ports may be configured as open-drain outputs.
In-System PROGRAMMING (ISP) WITH JTAG
   – Built-in JTAG compliant serial port allows full-chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ PAGE REGISTER
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
Programmable POWER MANAGEMENT
■ HIGH ENDURANCE:
   – 100,000 Erase/WRITE Cycles of Flash Memory
   – 1,000 Erase/WRITE Cycles of PLD
   – 15 Year Data Retention
■ 3.3V±10% SINGLE SUPPLY VOLTAGE
■ STANDBY CURRENT AS LOW AS 25µA
■ Packages are ECOPACK®

Part Name(s) : SMD1108 SMD1108F
Summit-Microelectronics
Summit Microelectronics
Description : 8-Channel Auto-Monitor™ ADC In System Programmable Analog (ISPA™) Device

INTRODUCTION
The SMD1108 is a versatile, Programmable 8-channel, 10-bit Data Acquisition System that is designed to operate autonomously, relieving the system host and logic board of the environmental monitoring tasks.
Programming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from Summit Microelectronics.

FEATURES
Programmable 8 Channel 10-Bit A to D converter
    ♦ Programmable Sequencing of Analog Switches in Auto-Monitor Mode
    ♦ Resolution of 10 bits
    ♦ Differential Non-Linearity of ±1LSB
    ♦ Top 4 Channels Programmable, Nonvolatile Upper/Lower IRQ Limits
    ♦ Bottom 4 Channels Tied to Matching Programmable, Nonvolatile Comparators
    ♦ 4 Companion Over-current Comparators
● Internal Temperature Sensor
Programmable LED Driver Outputs
Programmable, Nonvolatile Combinatorial Reset logic
● Nonvolatile Status Capture Register
● Two Programmable, Nonvolatile Watchdog Timers
● 1K-Bit Nonvolatile Memory
● Industry Standard 2-Wire Interface
    ♦ Nonvolatile Configuration Registers
    ♦ ADC Conversion Results
    ♦ Memory Array
    ♦ Mechanism for System Level Presence Detect

ICST
Integrated Circuit Systems
Description : Programmable System Clock Chip for AMD-K7™ processor

General Description
The ICS94235 is a main clock synthesizer chip for AMD-K7 based systems with ALI 1647 style chipsets. This provides all clocks required for such a system.

Features:
Programmable ouput frequency
Programmable ouput rise/fall time
Programmable CPU, SDRAM, PCI and AGP skew
• Real time system reset output
• Spread spectrum for EMI control typically by 7dB to 8dB, with Programmable spread percentage
• Watchdog timer technology to reset system if over-clocking causes malfunction
• Uses external 14.318MHz crystal

Output Features:
• 1 - Differential pair open drain CPU clocks
• 1 - Single-ended open drain CPU clock
• 13 - SDRAM @ 3.3V
• 7 - PCI @ 3.3V
• 2 - AGP @ 3.3V
• 1 - 48MHz, @3.3V
• 1 - REF @ 3.3V, (selectable strength) through I2C

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