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Part Name(s) : DV74AC112
AVG Semiconductors=>HITEK
AVG Semiconductors=>HITEK
Description : Dual JK negative edge-triggered flip-flop

Dual JK negative edge-triggered flip-flop

Part Name(s) : DV74AC109
AVG Semiconductors=>HITEK
AVG Semiconductors=>HITEK
Description : Dual JK Positive edge-triggered flip-flop

Dual JK Positive edge-triggered flip-flop

Part Name(s) : SN54LS107A
Motorola => Freescale
Motorola => Freescale
Description : Dual JK negative edge-triggered flip-flop

Dual JK negative edge-triggered flip-flop LOW POWER SCHOTTKY

The SN54/74LS107A is a Dual JK flip-flop with indiviDual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOWtransition of the clock. A LOW signal on CD input overrides the other inputs and makes the Q output LOW. The SN54 /74LS107A is the same as the SN54/74LS73A but has corner power pins.

Part Name(s) : MC74F109
Motorola => Freescale
Motorola => Freescale
Description : Dual JK POSITIVE edge-triggered flip-flop

Dual JK POSITIVE edge-triggered flip-flop

The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to F74 data sheet) by connecting the J and K inputs together.

Part Name(s) : MC74AC113
Motorola => Freescale
Motorola => Freescale
Description : Dual JK negative edge-triggered flip-flop

Dual JK negative edge-triggered flip-flop

The MC74AC113/74ACT113 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
   LOW input to SD (Set) sets Q to HIGH level
   Set is independent of clock
• Outputs Source/Sink 24 mA
• ′ACT113 Has TTL Compatible Inputs

Part Name(s) : SN54LS109AJ
Motorola => Freescale
Motorola => Freescale
Description : Dual JK POSITIVE edge-triggered flip-flop

Dual JK POSITIVE edge-triggered flip-flop LOW POWER SCHOTTKY



The SN54/74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by simply connecting the J and Kpins together.


Part Name(s) : GD4027B
Unspecified
Unspecified
Description : Dual JK flip-flop

DESCRIPTION
The GD4027B is a Dual JK flip-flop which is edge-triggered and features independent Direct Set, Direct Clear, and Clock inputs.

Part Name(s) : 74ALS112
Philips Electronics
Philips Electronics
Description : Dual J-K negative edge-triggered flip-flop

DESCRIPTION

The 74ALS112A, Dual negative edge-triggered JK-type flip-flop features indiviDual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs.

The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs.


Part Name(s) : 74LS114A
Motorola => Freescale
Motorola => Freescale
Description : Dual JK negative edge-triggered flip-flop

The SN54/74LS114A offers common clock and common clear inputs and indiviDual J, K, and set inputs. These monolithic Dual flip-flops are designed sothat when the clock goes HIGH, the inputs are enabled and data will be accepted.The logic level of the J and K inputs may be allowed to change when theclock pulse is HIGH and the bistable willperform according to the truth tableas long asminimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.


Part Name(s) : MC74AC112
Motorola => Freescale
Motorola => Freescale
Description : Dual JK negative edge-triggered flip-flop

Dual JK negative edge-triggered flip-flop

The MC74AC112/74ACT112 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
   LOW input to SD (Set) sets Q to HIGH level
   LOW input to CD (Clear) sets Q to LOW level
   Clear and Set are independent of clock
   Simultaneous LOW on CD and SD makes both Q and Q HIGH
  
• Outputs Source/Sink 24 mA
• ′ACT112 Has TTL Compatible Inputs

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