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Part Name(s) : THC63LVD823
THINE
THine Electronics, Inc.
Description : Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA

General Description
The THC63LVD823 Transmitter is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions.
   
Features
• Wide dot clock range: 25-135MHz suited for VGA,
    SVGA, XGA, SXGA, SXGA+ and UXGA
• PLL requires No external components
• Supports Dual Link, Dual-in (TTL)/Dual-out
    (LVDS) pixel up to 170MHz dot clock for UXGA
• Supports Single Link, Dual-in (TTL)/Single-out
    (LVDS) pixel up to 135MHz dot clock for SXGA+
• Supports Single Link, Single-in (TTL)/Single-out
    (LVDS) pixel up to 85MHz dot clock for XGA
• Clock edge selectable
• Supports Reduced swing LVDS for Low EMI
• Power down mode
• Low power single 3.3V CMOS design
• 100pin TQFP
• THC63LVDM83R compatible
   

ETC
Unspecified
Description : LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface

[NOVATEK]

General Description
The NT7181 Transmitter contains four 7-bit parallel-load serial-out registers, a 7x clock synthesizer, and five low-voltage differential (LVDS) line in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over four balanced-pair conductors for receipt by a compatible receiver, such as the DS90CF386 or THC63LVDF84A.The NT7181 Transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphic controllers. The NT7181 Transmitter can be programmed for rising edge strobe(RFB=1) or falling edge strobe(RFB=0) through the RFB pin. When transmitting, data bits D0 - D27 are each loaded into registers of the NT7181 on the rising edge or falling edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (TCLK) are then output to LVDS output drivers. The frequency of TCLK is the same as the input clock, CLKIN.
The NT7181 requires no external components and little or no control. The data bus appears the same at the input to the transmitting and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear ( PWDN ) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The NT7181 are characterized for operation over free-air temperature ranges of 0°C to 70°C.

Features
■ 28:4 Data Channel Compression at up to 297 Megabytes per Second Throughput
■ Suited for VGA, SVGA, XGA and Dual pixel SXGA, UXGA Display Data Transmission From Controller to Display With Very Low EMI
■ 28 Data Channels and Clock-In Low-Voltage TTL and 4 Data Channels and Clock-Out Low-Voltage Differential
■ Operates From a Single 3.3V Supply With 250mW (Typ)
■ Low profile 56 Lead TSSOP Package
■ Clock edge Programmable for Transmitter
■ Wide Phase-Lock Input Frequency Range: 25 MHz To 85 MHz
■ Supports Spread Spectrum Clock Generator
■ Suggests to use for LCD monitor only
■ No External Components Required for PLL

Novatek
Novatek Microelectronics
Description : LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface

General Description
The NT7181 Transmitter contains four 7-bit parallel-load serial-out registers, a 7x clock synthesizer, and five low-voltage differential (LVDS) line in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over four balanced-pair conductors for receipt by a compatible receiver, such as the DS90CF386 or THC63LVDF84A.The NT7181 Transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphic controllers. The NT7181 Transmitter can be programmed for rising edge strobe(RFB=1) or falling edge strobe(RFB=0) through the RFB pin. When transmitting, data bits D0 - D27 are each loaded into registers of the NT7181 on the rising edge or falling edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (TCLK) are then output to LVDS output drivers. The frequency of TCLK is the same as the input clock, CLKIN.
The NT7181 requires no external components and little or no control. The data bus appears the same at the input to the transmitting and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear ( PWDN ) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The NT7181 are characterized for operation over free-air temperature ranges of 0°C to 70°C.

Features
■ 28:4 Data Channel Compression at up to 297 Megabytes per Second Throughput
■ Suited for VGA, SVGA, XGA and Dual pixel SXGA, UXGA Display Data Transmission From Controller to Display With Very Low EMI
■ 28 Data Channels and Clock-In Low-Voltage TTL and 4 Data Channels and Clock-Out Low-Voltage Differential
■ Operates From a Single 3.3V Supply With 250mW (Typ)
■ Low profile 56 Lead TSSOP Package
■ Clock edge Programmable for Transmitter
■ Wide Phase-Lock Input Frequency Range: 25 MHz To 85 MHz
■ Supports Spread Spectrum Clock Generator
■ Suggests to use for LCD monitor only
■ No External Components Required for PLL

Description : Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers

General Description
The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low Voltage Differential Signaling) data streams. A phaselocked transmit clock is transmitted in parallel with the data stream over a separate LVDS Link. Every cycle of transmit clock 28 bits of input LVTTL data are sampled and transmitted.

Features
■ Low power consumption
■ 20 MHz to 85 MHz shift clock support
■ r1V common-mode range around 1.2V
■ Narrow bus reduces cable size and cost
■ High throughput (up to 2.38 Gbps throughput)
■ Internal PLL with no external component
■ Compatible with TIA/EIA-644 specification
■ Devices are offered 56-lead TSSOP packages

Fairchild
Fairchild Semiconductor
Description : Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer

Description
The FIN3385 and FIN3386 transform 28-bit wide parallel Low-Voltage TTL (LVTTL) data into four serial Low Voltage Differential Signaling (LVDS) data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS Link. Every cycle of transmit clock, 28-bits of input LVTTL data are sampled and transmitted.
The FIN3386 receives and converts the 4/3 serial LVDS data streams back into 28/21 bits of LVTTL data, acting as the deserializer.

Features
Operation -40°C to +85°C
Low Power Consumption
20MHz to 85MHz Shift Clock Support
±1V Common-Mode Range around 1.2V
Narrow Bus Reduces Cable Size and Cost
High Throughput (up to 2.38Gbps)
Internal PLL with No External Component
Compatible with TIA/EIA-644 Specification
56-Lead, TSSOP Package

Part Name(s) : RTD2010
Realtek
Realtek Semiconductor
Description : Flat Panel Display Controller

General Description
The Realtek RTD2010 is a highly-integrated single chip IC controller solution for producing real time, top quality digital video and computer graphic images on LCD monitor/Flat Panel Displays, such as XGA LCD monitors. LCD monitors and Flat Panel Displays provide a sharp, flicker free Display while saving space and energy for desktop PC applications. The RTD2010 provides an ideal interface between industry standard digital graphics controllers and a wide variety of LCD Panel devices. Flat Panel devices using the RTD2010 can support all incoming VESA modes and interface to any TFT LCD device, up to XGA (1024x768) resolution.

Part Name(s) : MX88L284AEC
ETC1
Unspecified
Description : Highly integration chip for Flat Panel Display application

[MXIC]

General Description
The MX88L284AEC is a highly integration chip for Flat Panel Display application. It’ s fully
compatible with MX88L284. With Macronix’ s SmartscalingTM -2 filter, it provides high quality
scaled video image and format conversion capability.

Features
General Features
·  Converts NTSC/PAL and PC video signal into Flat Panel Display device timing and resolution
·  Provide Full frame buffer, reduce frame buffer (w/ compression) and frame buffer less optional architecture.
·  Built-in memory and output clock generator
·  Built-in OSD generator with 64 ROM font, and 64 programmable RAM fonts
·  Provide 90 degree rotation for internal OSD to support portrait direction Display
·  Arbitrary scaling from 1/32 to 32 times with filters (SmartScalingTM – 2+ Technology)
·  Support Auto-tracking and Auto-position capabilities (SmartTrackingTM Technology)
·  Support Auto-gain capability for input image
·  Support Flip and Mirror capabilities
·  On-chip brightness and contrast adjustments
·  On-chip gcorrection for Panel compensation
·  Support dynamic dithering capability to make 18 bit video as good as 24 bit quality
·  Support H/V Sync. Polarity and pulse width information for mode detection
·  Support two types of CPU interface (direct and serial bus)

Applications
·  LCD monitor
·  LCD projector
·  Other Flat Panel Display Application (DMD, PDP, PALC … )

Description : Long Distance Digital Display Link Transmitter & Receiver

[Inova Semiconductors]

General Description
The GigaSTaR® Digital Display Link is a high-speed serial and long distance Link for video, audio and digital data, which supports the popular VESA standard but also proprietary video formats from VGA to UXGA with color depth up to 24 bits.

Features:
• Supported VESA video resolutions:
    − INDT/R165B: VGA … XGA
    − INDT/R330B: VGA … UXGA
• Flexible parallel graphics controller and LC-Display interfaces:
    − 12-bit (½ pixel/clock) – Tx only
    − 18- / 24-Bit (1 pixel/clock)
    − 36- / 48-bit (2 pixel/clock)
• Flexible pixel data clocking on rising/falling/both clock edges
• Pixel Clock frequency: 24 – 161 MHz
• Easy adaptation to DVI and LDI/LVDS through standard interface devices
• 4 channel audio interface (IEC958 compliant S/PDIF)
• High- and low-speed bi-directional sideband data channels
• Single + 3.3 V power supply
• Extended temperature range: -40 – +85 °C

Applications:
• Long distance multimedia consoles
• High resolution industrial remote terminals
• Video broadcast systems
• Long distance camera Links
• Machine vision systems
• Car navigation & telematics systems
• Digital TV equipment
• Video Projectors
• Home Cinemas

Part Name(s) : THC63LVD103
THINE
THine Electronics, Inc.
Description : 135MHz 30Bits COLOR LVDS Transmitter

General Description
The THC63LVD103 Transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVD103 converts 35bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. The Transmitter can be programmed for ris ing edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 135MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmit ted at an effective rate of 945Mbps per LVDS channel.

Features
• Wide dot clock range: 8-135MHz suited for NTSC, VGA, SVGA, XGA,SXGA and SXGA+
• PLL requires no external components
• Supports spread spectrum clock generator
• On chip jitter filtering
• Clock edge selectable
• Supports reduced swing LVDS for low EMI
• Power down mode
• Low power single 3.3V CMOS design
• 64pin TQFP
• Backward compatible with THC63LVDM63R(18bits) / M83R(24bits)

Part Name(s) : THC63LVD103D
THINE
THine Electronics, Inc.
Description : 160MHz 30Bits COLOR LVDS Transmitter

General Description
The THC63LVD103D Transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to 1080p(60Hz). The THC63LVD103D converts 35bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. The Transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 160MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmit ted at an effective rate of 1.12Gbps per LVDS channel.

Features
• Wide dot clock range: 8-160MHz suited for NTSC, VGA, SVGA, XGA,SXGA and SXGA+ and 1080p
• PLL requires no external components
• Supports spread spectrum clock generator
• On chip jitter filtering
• Clock edge selectable
• Supports reduced swing LVDS for low EMI
• Power down mode
• Low power single 3.3V CMOS design
• 64pin TQFP
• Pin compatible with THC63LVD103(30bits)

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