description
The TLC7528C, TLC7528E, and TLC7528I are dual, 8-bit, digital-to-analog converters designed with separate on-chip data latches and feature exceptionally close DAC-to-DAC matching.

Easily Interfaced to Microprocessors
On-Chip Data Latches
Monotonic Over the Entire A/D Conversion Range
Interchangeable With Analog Devices AD7528 and PMI PM-7528
Fast Control Signaling for Digital Signal Processor (DSP) Applications Including Interface With TMS320
Voltage-Mode Operation
CMOS Technology
 

description
The TLC7524C, TLC7524E, and TLC7524I are CMOS, 8-bit, digital-to-analog converters (DACs) designed for easy interface to most popular microprocessors.
The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits, which produce the highest glitch impulse. The devices provide accuracy to 1/2LSB without the need for thin-film resistors or laser trimming, while dissipating less than 5mW typically.
Featuring operation from a 5V to 15V single supply, these devices interface easily to most microprocessor buses or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many microprocessor-controlled gain-setting and signal-control applications.

• Easily Interfaced to Microprocessors
• On-Chip Data Latches
• Monotonic Over the Entire A/D Conversion Range
• Segmented High-Order Bits Ensure Low-Glitch Output
• Interchangeable With Analog Devices AD7524, PMI PM-7524, and Micro Power Systems MP7524
• Fast Control Signaling for Digital Signal-Processor Applications Including Interface With TMS320
• CMOS Technology

Description
The ’HC154 and ’HCT154 are 4- to 16-line decoders/demultiplexers with two enable inputs, E1 and E2. A High on either enable input forces the output into the High state. The demultiplexing function is performed by using the four input lines, A0 to A3, to select the output lines Y0 to Y15, and using one enable as the data input while holding the other enable low.

Features
• Two Enable Inputs to Facilitate Demultiplexing and
   Cascading Functions
• Fanout (Over Temperature Range)
   - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
   Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
      VCC = 5V
• HCT Types
   - 4.5V to 5.5V Operation
   - Direct LSTTL Input Logic Compatibility,
      VIL= 0.8V (Max), VIH = 2V (Min)
   - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH

description
The CD74HCT4514 and CD74HCT4515 are high-speed silicon-gate devices consisting of a 4-bit strobed latch and a 4-line to 16-line decoder. The selected output is enabled by a low on the enable (E) input. A high on E inhibits selection of any output. Demultiplexing is accomplished by using E as the data input and the select inputs (A0−A3) as addresses. E also serves as a chip select when these devices are cascaded. When the latch enable (LE) is high, the output follows changes in the inputs (see decode function table). When LE is low, the output is isolated from changes in the input and remains at the level (high for the ’4514, low for the ’4515) it had before the latch was enabled.

4.5-V to 5.5-V VCC Operation

Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus-Driver Outputs . . . 15 LSTTL Loads

Wide Operating Temperature Range of −55°C to 125°C
Balanced Propagation Delays and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HCT Types
− Direct LSTTL Input Logic Compatibility, VIL = 0.8 V (Max), VIH = 2 V (Min)
− CMOS Input Compatibility, II ≤ 1 µA at VOL, VOH

Description
The CD54HC4514, CD74HC4514, and CD74HC4515 are high-speed silicon gate devices consisting of a 4-bit strobed latch and a 4- to 16-line decoder. The selected output is enabled by a low on the enable input (E). A high onE inhibits selection of any output. Demultiplexing is accomplished by using theE input as the data input and the select inputs (A0-A3) as addresses. ThisE input also serves as a chip select when these devices are cascaded.

Features
• Multifunction Capability
   - Binary to 1-of-16 Decoder
   - 1-to-16 Line Demultiplexer
• Fanout (Over Temperature Range)
   - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: NIL= 30%, NIH= 30% of VCC at VCC= 5V

Description
The ’HC154 and ’HCT154 are 4- to 16-line decoders/demultiplexers with two enable inputs, E1 and E2. A High on either enable input forces the output into the High state. The demultiplexing function is performed by using the four input lines, A0 to A3, to select the output lines Y0 to Y15, and using one enable as the data input while holding the other enable low.

Features
• Two Enable Inputs to Facilitate Demultiplexing and
   Cascading Functions
• Fanout (Over Temperature Range)
   - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
   Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
      VCC = 5V
• HCT Types
   - 4.5V to 5.5V Operation
   - Direct LSTTL Input Logic Compatibility,
      VIL= 0.8V (Max), VIH = 2V (Min)
   - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH

Description
The CD54HC4514, CD74HC4514, and CD74HC4515 are high-speed silicon gate devices consisting of a 4-bit strobed latch and a 4- to 16-line decoder. The selected output is enabled by a low on the enable input (E). A high onE inhibits selection of any output. Demultiplexing is accomplished by using theE input as the data input and the select inputs (A0-A3) as addresses. ThisE input also serves as a chip select when these devices are cascaded.

Features
• Multifunction Capability
   - Binary to 1-of-16 Decoder
   - 1-to-16 Line Demultiplexer
• Fanout (Over Temperature Range)
   - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: NIL= 30%, NIH= 30% of VCC at VCC= 5V