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DM74LS112ACW

  

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Fairchild
Fairchild Semiconductor
DM74LS112ACW Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated.


other parts : 74LS112  74LS112A  DM74LS112A  DM74LS112AM  DM74LS112AMX  DM74LS112AN  
DM74LS112ACW PDF

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