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ADF4001BCP

  

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ADI
Analog Devices
ADF4001BCP 200 MHz Clock Generator PLL

GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator) or VCXO (voltage controlled crystal oscillator). The N minimum value of 1 allows flexibility in clock generation.

FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead LFCSP

APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM


other parts : ADF4001  ADF4001BCPZ  ADF4001BCPZ-RL  ADF4001BCPZ-RL7  ADF4001BRU  ADF4001BRU-REEL  ADF4001BRU-REEL7  ADF4001BRUZ  ADF4001BRUZ-R7  ADF4001BRUZ-RL  
ADF4001BCP PDF
ADI
Analog Devices
ADF4001BCPZ 200 MHz Clock Generator PLL

GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator) or VCXO (voltage controlled crystal oscillator). The N minimum value of 1 allows flexibility in clock generation.

FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead LFCSP

APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM


other parts : ADF4001  ADF4001BCP  ADF4001BCPZ-RL  ADF4001BCPZ-RL7  ADF4001BRU  ADF4001BRU-REEL  ADF4001BRU-REEL7  ADF4001BRUZ  ADF4001BRUZ-R7  ADF4001BRUZ-RL  
ADF4001BCPZ PDF
ADI
Analog Devices
ADF4001BCPZ-RL 200 MHz Clock Generator PLL

GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator) or VCXO (voltage controlled crystal oscillator). The N minimum value of 1 allows flexibility in clock generation.

FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead LFCSP

APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM


other parts : ADF4001  ADF4001BCP  ADF4001BCPZ  ADF4001BCPZ-RL7  ADF4001BRU  ADF4001BRU-REEL  ADF4001BRU-REEL7  ADF4001BRUZ  ADF4001BRUZ-R7  ADF4001BRUZ-RL  
ADF4001BCPZ-RL PDF
ADI
Analog Devices
ADF4001BCPZ-RL7 200 MHz Clock Generator PLL

GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator) or VCXO (voltage controlled crystal oscillator). The N minimum value of 1 allows flexibility in clock generation.

FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead LFCSP

APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM


other parts : ADF4001  ADF4001BCP  ADF4001BCPZ  ADF4001BCPZ-RL  ADF4001BRU  ADF4001BRU-REEL  ADF4001BRU-REEL7  ADF4001BRUZ  ADF4001BRUZ-R7  ADF4001BRUZ-RL  
ADF4001BCPZ-RL7 PDF

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