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54AC16620

  

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TI
Texas Instruments
54AC16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

description
The ’AC16620 are inverting 16-bit transceivers designed for asynchronous communication between data buses. The control-function implementation allows for maximum flexibility in timing.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the complementary output-enable (OEAB or OEBA) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.

• Members of the Texas Instruments Widebus Family
• 3-State Outputs Drive Bus Lines Directly
• Flow-Through Architecture Optimizes PCB Layout
• Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic 300-mil
   Shrink Small-Outline (DL) Packages Using
   25-mil Center-to-Center Pin Spacings and
   380-mil Fine-Pitch Ceramic Flat (WD)
   Packages Using 25-mil Center-to-Center
   Pin Spacings

 


other parts : 54AC16620WD  74AC16620  74AC16620DL  74AC16620DLR  
54AC16620 PDF
TI
Texas Instruments
54AC16620WD 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

description
The ’AC16620 are inverting 16-bit transceivers designed for asynchronous communication between data buses. The control-function implementation allows for maximum flexibility in timing.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the complementary output-enable (OEAB or OEBA) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.

• Members of the Texas Instruments Widebus Family
• 3-State Outputs Drive Bus Lines Directly
• Flow-Through Architecture Optimizes PCB Layout
• Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic 300-mil
   Shrink Small-Outline (DL) Packages Using
   25-mil Center-to-Center Pin Spacings and
   380-mil Fine-Pitch Ceramic Flat (WD)
   Packages Using 25-mil Center-to-Center
   Pin Spacings

 


other parts : 54AC16620  74AC16620  74AC16620DL  74AC16620DLR  
54AC16620WD PDF

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