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SN74LVC1G86

  

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TI
Texas Instruments
SN74LVC1G86 Single 2-Input Exclusive-OR Gate

Description
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum t pd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Features
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At 85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back Drive Protection
• Available in the Texas Instruments NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio


other parts : SN74LVC1G86DBV  SN74LVC1G86DCK  SN74LVC1G86DRL  SN74LVC1G86YZP  SN74LVC1G86DBVR  SN74LVC1G86DBVRE4  SN74LVC1G86DBVRG4  SN74LVC1G86DBVT  SN74LVC1G86DCKR  SN74LVC1G86DCKRE4  
SN74LVC1G86 PDF
TI
Texas Instruments
SN74LVC1G86DCK Single 2-Input Exclusive-OR Gate

Description
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum t pd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Features
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At 85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back Drive Protection
• Available in the Texas Instruments NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio


other parts : SN74LVC1G86  SN74LVC1G86DBV  SN74LVC1G86DRL  SN74LVC1G86YZP  SN74LVC1G86DBVR  SN74LVC1G86DBVRE4  SN74LVC1G86DBVRG4  SN74LVC1G86DBVT  SN74LVC1G86DCKR  SN74LVC1G86DCKRE4  
SN74LVC1G86DCK PDF
TI
Texas Instruments
SN74LVC1G86YZP Single 2-Input Exclusive-OR Gate

Description
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum t pd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Features
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At 85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back Drive Protection
• Available in the Texas Instruments NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio


other parts : SN74LVC1G86  SN74LVC1G86DBV  SN74LVC1G86DCK  SN74LVC1G86DRL  SN74LVC1G86DBVR  SN74LVC1G86DBVRE4  SN74LVC1G86DBVRG4  SN74LVC1G86DBVT  SN74LVC1G86DCKR  SN74LVC1G86DCKRE4  
SN74LVC1G86YZP PDF
TI
Texas Instruments
SN74LVC1G86-EP SINGLE 2-INPUT EXCLUSIVE-OR GATE

DESCRIPTION/ORDERING INFORMATION
This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

FEATURES
• Controlled Baseline
   – One Assembly/Test Site, One Fabrication Site
• Extended Temperature Performance of -55°C to 125°C
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• QualificationPedigree (1)
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 6.7 ns at 3.3 V
• Low Power Consumption, 15-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 200-V Machine Model (A115-A)
   – 1000-V Charged-Device Model (C101)


other parts : SN74LVC1G86MDCKREP  V62/06666-01XE  
SN74LVC1G86-EP PDF
TI
Texas Instruments
SN74LVC1G86DRL Single 2-Input Exclusive-OR Gate

Description
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum t pd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Features
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At 85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back Drive Protection
• Available in the Texas Instruments NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio


other parts : SN74LVC1G86  SN74LVC1G86DBV  SN74LVC1G86DCK  SN74LVC1G86YZP  SN74LVC1G86DBVR  SN74LVC1G86DBVRE4  SN74LVC1G86DBVRG4  SN74LVC1G86DBVT  SN74LVC1G86DCKR  SN74LVC1G86DCKRE4  
SN74LVC1G86DRL PDF
TI
Texas Instruments
SN74LVC1G86DBV Single 2-Input Exclusive-OR Gate

Description
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum t pd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Features
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At 85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back Drive Protection
• Available in the Texas Instruments NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio


other parts : SN74LVC1G86  SN74LVC1G86DCK  SN74LVC1G86DRL  SN74LVC1G86YZP  SN74LVC1G86DBVR  SN74LVC1G86DBVRE4  SN74LVC1G86DBVRG4  SN74LVC1G86DBVT  SN74LVC1G86DCKR  SN74LVC1G86DCKRE4  
SN74LVC1G86DBV PDF
TI
Texas Instruments
SN74LVC1G86DRLR Single 2-Input Exclusive-OR Gate

Description
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum t pd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Features
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At 85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back Drive Protection
• Available in the Texas Instruments NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio


other parts : SN74LVC1G86  SN74LVC1G86DBV  SN74LVC1G86DCK  SN74LVC1G86DRL  SN74LVC1G86YZP  SN74LVC1G86DBVR  SN74LVC1G86DBVRE4  SN74LVC1G86DBVRG4  SN74LVC1G86DBVT  SN74LVC1G86DCKR  
SN74LVC1G86DRLR PDF
TI
Texas Instruments
SN74LVC1G86DBVR Single 2-Input Exclusive-OR Gate

Description
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum t pd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Features
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At 85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back Drive Protection
• Available in the Texas Instruments NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio


other parts : SN74LVC1G86  SN74LVC1G86DBV  SN74LVC1G86DCK  SN74LVC1G86DRL  SN74LVC1G86YZP  SN74LVC1G86DBVRE4  SN74LVC1G86DBVRG4  SN74LVC1G86DBVT  SN74LVC1G86DCKR  SN74LVC1G86DCKRE4  
SN74LVC1G86DBVR PDF
TI
Texas Instruments
SN74LVC1G86DCKR Single 2-Input Exclusive-OR Gate

Description
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum t pd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Features
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At 85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back Drive Protection
• Available in the Texas Instruments NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio


other parts : SN74LVC1G86  SN74LVC1G86DBV  SN74LVC1G86DCK  SN74LVC1G86DRL  SN74LVC1G86YZP  SN74LVC1G86DBVR  SN74LVC1G86DBVRE4  SN74LVC1G86DBVRG4  SN74LVC1G86DBVT  SN74LVC1G86DCKRE4  
SN74LVC1G86DCKR PDF
TI
Texas Instruments
SN74LVC1G86DBVT Single 2-Input Exclusive-OR Gate

Description
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum t pd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Features
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At 85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back Drive Protection
• Available in the Texas Instruments NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio


other parts : SN74LVC1G86  SN74LVC1G86DBV  SN74LVC1G86DCK  SN74LVC1G86DRL  SN74LVC1G86YZP  SN74LVC1G86DBVR  SN74LVC1G86DBVRE4  SN74LVC1G86DBVRG4  SN74LVC1G86DCKR  SN74LVC1G86DCKRE4  
SN74LVC1G86DBVT PDF
TI
Texas Instruments
SN74LVC1G86DCKT Single 2-Input Exclusive-OR Gate

Description
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum t pd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Features
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At 85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back Drive Protection
• Available in the Texas Instruments NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio


other parts : SN74LVC1G86  SN74LVC1G86DBV  SN74LVC1G86DCK  SN74LVC1G86DRL  SN74LVC1G86YZP  SN74LVC1G86DBVR  SN74LVC1G86DBVRE4  SN74LVC1G86DBVRG4  SN74LVC1G86DBVT  SN74LVC1G86DCKR  
SN74LVC1G86DCKT PDF
TI
Texas Instruments
SN74LVC1G86YZPR Single 2-Input Exclusive-OR Gate

Description
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum t pd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

Features
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At 85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back Drive Protection
• Available in the Texas Instruments NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio


other parts : SN74LVC1G86  SN74LVC1G86DBV  SN74LVC1G86DCK  SN74LVC1G86DRL  SN74LVC1G86YZP  SN74LVC1G86DBVR  SN74LVC1G86DBVRE4  SN74LVC1G86DBVRG4  SN74LVC1G86DBVT  SN74LVC1G86DCKR  
SN74LVC1G86YZPR PDF

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