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ST-Microelectronics
STMicroelectronics
PSD4235G2 Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based ap plications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O:
■ Dual Bank Flash Memories
   – 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
   – 256 Kbit Secondary Flash Memory with 4 sectors
   – Concurrent operation: read from one memory while erasing and writing the other
■ 64 Kbit SRAM (Battery Backed)
■ PLD with macrocells
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD – user defined internal chip select decoding
■ Seven l/O Ports with 52 I/O pins
   – 52 individually configurable I/O port pins that can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function l/Os – l/O ports may be configured as open-drain outputs
■ In-System Programming (ISP) with JTAG
   – Built-in JTAG compliant serial port allows full chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ Page Register
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 EraseWrite Cycles of PLD
   – 15 Year Data Retention
■ Single Supply Voltage
   – 5V ±10%
■ Memory Speed
   – 70ns Flash memory and SRAM access time


other parts : PSD4201F1-12U  PSD4201F1-12UI  PSD4201F1-15U  PSD4201F1-15UI  PSD4201F1-20U  PSD4201F1-20UI  PSD4201F1-70U  PSD4201F1-70UI  PSD4201F1-90U  PSD4201F1-90UI  
PSD4235G2 PDF
ST-Microelectronics
STMicroelectronics
PSD4235G2V Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply

SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based ap plications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O:
■ Dual Bank Flash Memories
   – 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
   – 256 Kbit Secondary Flash Memory with 4 sectors
   – Concurrent operation: read from one memory while erasing and writing the other
■ 64 Kbit SRAM (Battery Backed)
■ PLD with macrocells
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD – user defined internal chip select decoding
■ Seven l/O Ports with 52 I/O pins
   – 52 individually configurable I/O port pins that can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function l/Os – l/O ports may be configured as open-drain outputs
■ In-System Programming (ISP) with JTAG
   – Built-in JTAG compliant serial port allows full chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ Page Register
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 EraseWrite Cycles of PLD
   – 15 Year Data Retention
■ Single Supply Voltage
   – 5V ±10%
■ Memory Speed
   – 70ns Flash memory and SRAM access time

PSD4235G2V PDF
ST-Microelectronics
STMicroelectronics
PSD4235G2_02 Flash In-System-Programmable Peripherals for 16-Bit MCUs

Introduction
The PSD4000 series of Programmable Microcontroller (MCU) Peripherals brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD4000 devices combine many of the peripheral functions found in MCU based applications:
   • 4 Mbit of Flash memory
   • A secondary Flash memory for boot or data
   • Over 3,000 gates of Flash programmable logic
   • 64 Kbit SRAM
   • Reconfigurable I/O ports
   • Programmable power management.
  
FEATURES SUMMARY
■ 5 V±10% Single Supply Voltage:
■ Up to 4 Mbit of Primary Flash Memory (8 uniform sectors)
■ 256Kbit Secondary Flash Memory (4 uniform sectors)
■ Up to 64 Kbit SRAM
■ Over 3,000 Gates of PLD: DPLD and CPLD
■ 52 Reconfigurable I/O ports
■ Enhanced JTAG Serial Port
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 Erase/Write Cycles of PLD


other parts : PSD4135G2-15J  PSD4135G2-15JI  PSD4135G2-15M  PSD4135G2-15MI  PSD4135G2-15U  PSD4135G2-15UI  PSD4135G2-20B81  PSD4135G2-70JI  PSD4135G2  PSD4135G2-90U  
PSD4235G2_02 PDF
ST-Microelectronics
STMicroelectronics
PSD4235G2-20U Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based ap plications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O:
■ Dual Bank Flash Memories
   – 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
   – 256 Kbit Secondary Flash Memory with 4 sectors
   – Concurrent operation: read from one memory while erasing and writing the other
■ 64 Kbit SRAM (Battery Backed)
■ PLD with macrocells
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD – user defined internal chip select decoding
■ Seven l/O Ports with 52 I/O pins
   – 52 individually configurable I/O port pins that can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function l/Os – l/O ports may be configured as open-drain outputs
■ In-System Programming (ISP) with JTAG
   – Built-in JTAG compliant serial port allows full chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ Page Register
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 EraseWrite Cycles of PLD
   – 15 Year Data Retention
■ Single Supply Voltage
   – 5V ±10%
■ Memory Speed
   – 70ns Flash memory and SRAM access time


other parts : PSD4201F1-12U  PSD4201F1-12UI  PSD4201F1-15U  PSD4201F1-15UI  PSD4201F1-20U  PSD4201F1-20UI  PSD4201F1-70U  PSD4201F1-70UI  PSD4201F1-90U  PSD4201F1-90UI  
PSD4235G2-20U PDF
ST-Microelectronics
STMicroelectronics
PSD4235G2-70U Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based ap plications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O:
■ Dual Bank Flash Memories
   – 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
   – 256 Kbit Secondary Flash Memory with 4 sectors
   – Concurrent operation: read from one memory while erasing and writing the other
■ 64 Kbit SRAM (Battery Backed)
■ PLD with macrocells
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD – user defined internal chip select decoding
■ Seven l/O Ports with 52 I/O pins
   – 52 individually configurable I/O port pins that can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function l/Os – l/O ports may be configured as open-drain outputs
■ In-System Programming (ISP) with JTAG
   – Built-in JTAG compliant serial port allows full chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ Page Register
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 EraseWrite Cycles of PLD
   – 15 Year Data Retention
■ Single Supply Voltage
   – 5V ±10%
■ Memory Speed
   – 70ns Flash memory and SRAM access time


other parts : PSD4201F1-12U  PSD4201F1-12UI  PSD4201F1-15U  PSD4201F1-15UI  PSD4201F1-20U  PSD4201F1-20UI  PSD4201F1-70U  PSD4201F1-70UI  PSD4201F1-90U  PSD4201F1-90UI  
PSD4235G2-70U PDF
ST-Microelectronics
STMicroelectronics
PSD4235G2-15U Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based ap plications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O:
■ Dual Bank Flash Memories
   – 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
   – 256 Kbit Secondary Flash Memory with 4 sectors
   – Concurrent operation: read from one memory while erasing and writing the other
■ 64 Kbit SRAM (Battery Backed)
■ PLD with macrocells
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD – user defined internal chip select decoding
■ Seven l/O Ports with 52 I/O pins
   – 52 individually configurable I/O port pins that can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function l/Os – l/O ports may be configured as open-drain outputs
■ In-System Programming (ISP) with JTAG
   – Built-in JTAG compliant serial port allows full chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ Page Register
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 EraseWrite Cycles of PLD
   – 15 Year Data Retention
■ Single Supply Voltage
   – 5V ±10%
■ Memory Speed
   – 70ns Flash memory and SRAM access time


other parts : PSD4201F1-12U  PSD4201F1-12UI  PSD4201F1-15U  PSD4201F1-15UI  PSD4201F1-20U  PSD4201F1-20UI  PSD4201F1-70U  PSD4201F1-70UI  PSD4201F1-90U  PSD4201F1-90UI  
PSD4235G2-15U PDF
ST-Microelectronics
STMicroelectronics
PSD4235G2-12U Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based ap plications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O:
■ Dual Bank Flash Memories
   – 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
   – 256 Kbit Secondary Flash Memory with 4 sectors
   – Concurrent operation: read from one memory while erasing and writing the other
■ 64 Kbit SRAM (Battery Backed)
■ PLD with macrocells
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD – user defined internal chip select decoding
■ Seven l/O Ports with 52 I/O pins
   – 52 individually configurable I/O port pins that can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function l/Os – l/O ports may be configured as open-drain outputs
■ In-System Programming (ISP) with JTAG
   – Built-in JTAG compliant serial port allows full chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ Page Register
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 EraseWrite Cycles of PLD
   – 15 Year Data Retention
■ Single Supply Voltage
   – 5V ±10%
■ Memory Speed
   – 70ns Flash memory and SRAM access time


other parts : PSD4201F1-12U  PSD4201F1-12UI  PSD4201F1-15U  PSD4201F1-15UI  PSD4201F1-20U  PSD4201F1-20UI  PSD4201F1-70U  PSD4201F1-70UI  PSD4201F1-90U  PSD4201F1-90UI  
PSD4235G2-12U PDF
ST-Microelectronics
STMicroelectronics
PSD4235G2-90U Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based ap plications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O:
■ Dual Bank Flash Memories
   – 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
   – 256 Kbit Secondary Flash Memory with 4 sectors
   – Concurrent operation: read from one memory while erasing and writing the other
■ 64 Kbit SRAM (Battery Backed)
■ PLD with macrocells
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD – user defined internal chip select decoding
■ Seven l/O Ports with 52 I/O pins
   – 52 individually configurable I/O port pins that can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function l/Os – l/O ports may be configured as open-drain outputs
■ In-System Programming (ISP) with JTAG
   – Built-in JTAG compliant serial port allows full chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ Page Register
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 EraseWrite Cycles of PLD
   – 15 Year Data Retention
■ Single Supply Voltage
   – 5V ±10%
■ Memory Speed
   – 70ns Flash memory and SRAM access time


other parts : PSD4201F1-12U  PSD4201F1-12UI  PSD4201F1-15U  PSD4201F1-15UI  PSD4201F1-20U  PSD4201F1-20UI  PSD4201F1-70U  PSD4201F1-70UI  PSD4201F1-90U  PSD4201F1-90UI  
PSD4235G2-90U PDF
ST-Microelectronics
STMicroelectronics
PSD4235G2V-20U Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based ap plications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O:
■ Dual Bank Flash Memories
   – 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
   – 256 Kbit Secondary Flash Memory with 4 sectors
   – Concurrent operation: read from one memory while erasing and writing the other
■ 64 Kbit SRAM (Battery Backed)
■ PLD with macrocells
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD – user defined internal chip select decoding
■ Seven l/O Ports with 52 I/O pins
   – 52 individually configurable I/O port pins that can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function l/Os – l/O ports may be configured as open-drain outputs
■ In-System Programming (ISP) with JTAG
   – Built-in JTAG compliant serial port allows full chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ Page Register
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 EraseWrite Cycles of PLD
   – 15 Year Data Retention
■ Single Supply Voltage
   – 5V ±10%
■ Memory Speed
   – 70ns Flash memory and SRAM access time


other parts : PSD4201F1-12U  PSD4201F1-12UI  PSD4201F1-15U  PSD4201F1-15UI  PSD4201F1-20U  PSD4201F1-20UI  PSD4201F1-70U  PSD4201F1-70UI  PSD4201F1-90U  PSD4201F1-90UI  
PSD4235G2V-20U PDF
ST-Microelectronics
STMicroelectronics
PSD4235G2-90UT Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based ap plications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O:
■ Dual Bank Flash Memories
   – 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
   – 256 Kbit Secondary Flash Memory with 4 sectors
   – Concurrent operation: read from one memory while erasing and writing the other
■ 64 Kbit SRAM (Battery Backed)
■ PLD with macrocells
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD – user defined internal chip select decoding
■ Seven l/O Ports with 52 I/O pins
   – 52 individually configurable I/O port pins that can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function l/Os – l/O ports may be configured as open-drain outputs
■ In-System Programming (ISP) with JTAG
   – Built-in JTAG compliant serial port allows full chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ Page Register
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 EraseWrite Cycles of PLD
   – 15 Year Data Retention
■ Single Supply Voltage
   – 5V ±10%
■ Memory Speed
   – 70ns Flash memory and SRAM access time


other parts : PSD4201G1-70UT  PSD4201G1-70UIT  PSD4201G1-90UT  PSD4201G1-90UIT  PSD4201G1-12UT  PSD4201G1-12UIT  PSD4201G1-15UT  PSD4201G1-15UIT  PSD4201G1-20UT  PSD4201G1-20UIT  
PSD4235G2-90UT PDF
ST-Microelectronics
STMicroelectronics
PSD4235G2-20UT Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based ap plications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O:
■ Dual Bank Flash Memories
   – 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
   – 256 Kbit Secondary Flash Memory with 4 sectors
   – Concurrent operation: read from one memory while erasing and writing the other
■ 64 Kbit SRAM (Battery Backed)
■ PLD with macrocells
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD – user defined internal chip select decoding
■ Seven l/O Ports with 52 I/O pins
   – 52 individually configurable I/O port pins that can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function l/Os – l/O ports may be configured as open-drain outputs
■ In-System Programming (ISP) with JTAG
   – Built-in JTAG compliant serial port allows full chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ Page Register
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 EraseWrite Cycles of PLD
   – 15 Year Data Retention
■ Single Supply Voltage
   – 5V ±10%
■ Memory Speed
   – 70ns Flash memory and SRAM access time


other parts : PSD4201G1-70UT  PSD4201G1-70UIT  PSD4201G1-90UT  PSD4201G1-90UIT  PSD4201G1-12UT  PSD4201G1-12UIT  PSD4201G1-15UT  PSD4201G1-15UIT  PSD4201G1-20UT  PSD4201G1-20UIT  
PSD4235G2-20UT PDF
ST-Microelectronics
STMicroelectronics
PSD4235G2-90UI Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based ap plications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O:
■ Dual Bank Flash Memories
   – 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
   – 256 Kbit Secondary Flash Memory with 4 sectors
   – Concurrent operation: read from one memory while erasing and writing the other
■ 64 Kbit SRAM (Battery Backed)
■ PLD with macrocells
   – Over 3000 Gates of PLD: CPLD and DPLD
   – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
   – DPLD – user defined internal chip select decoding
■ Seven l/O Ports with 52 I/O pins
   – 52 individually configurable I/O port pins that can be used for the following functions:
   – MCU I/Os
   – PLD I/Os
   – Latched MCU address output
   – Special function l/Os – l/O ports may be configured as open-drain outputs
■ In-System Programming (ISP) with JTAG
   – Built-in JTAG compliant serial port allows full chip In-System Programmability
   – Efficient manufacturing allow easy product testing and programming
   – Use low cost FlashLINK cable with PC
■ Page Register
   – Internal page register that can be used to expand the microcontroller address space by a factor of 256
■ Programmable power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 EraseWrite Cycles of PLD
   – 15 Year Data Retention
■ Single Supply Voltage
   – 5V ±10%
■ Memory Speed
   – 70ns Flash memory and SRAM access time


other parts : PSD4201F1-12U  PSD4201F1-12UI  PSD4201F1-15U  PSD4201F1-15UI  PSD4201F1-20U  PSD4201F1-20UI  PSD4201F1-70U  PSD4201F1-70UI  PSD4201F1-90U  PSD4201F1-90UI  
PSD4235G2-90UI PDF

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