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Micron
Micron Technology
MT49H16M16 REDUCED LATENCY DRAM (RLDRAM®)

General Description
The Micron® 256Mb reduced latency DRAM (RLDRAM®) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) form at where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for high bandwidth communication data storage—telecommunications, networking, and cache applications, etc.

Features
• Organization 8 Meg x 32, 16 Meg x 16 in 8 banks
• Cyclic bank addressing for maximum data bandwidth
• Non multiplexed addresses
• Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR
• Up to 600 Mb/sec/pin data rate
• Programmable READ latency (RL) of 5-6
• Data valid signal (DVLD) activated as read data is available
• Data mask signals (DM0/DM1) to mask first and
• second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Pseudo-HSTL 1.8V I/O Supply
• Internal auto precharge
• Refresh requirements: 32ms at 95°C case
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)
• 144-pin, 11mm x 18.5mm µBGA package


other parts : MT49H16M16FM-XX  MT49H8M32  MT49H8M32FM-XX  MT49H8M32FM-33  MT49H8M32FM-33IT  MT49H8M32FM-4  MT49H8M32FM-4IT  MT49H8M32FM-5  MT49H8M32FM-5IT  MT49H8M32BM-33  
MT49H16M16 PDF
Micron
Micron Technology
MT49H16M16_2002 REDUCED LATENCY DRAM (RLDRAM®)

GENERAL DESCRIPTION
The Micron® 256Mb Reduced Latency DRAM (RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for communication data storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache applications requiring large amounts of memory.

FEATURES
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Cyclic bank addressing for maximum data out bandwidth
• Non-multiplexed addresses
• Non-interruptible sequential burst of two (2-bit
   prefetch) and four (4-bit prefetch) DDR
• Target 600 Mb/s/p data rate
• Programmable Read Latency (RL) of 5-8
• Data valid signal (DVLD) activated as read data is available
• Data Mask signals (DM0/DM1) to mask first and
   second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• Pseudo-HSTL 1.8V I/O Supply
• Internal Auto Precharge
• Refresh requirements: 32ms at 100°C junction
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)


other parts : MT49H16M16FM-XX_2002  MT49H8M32_2002  MT49H8M32FM-XX_2002  MT49H8M32FM-3.3_2002  MT49H8M32FM-4_2002  MT49H8M32FM-5_2002  MT49H16M16FM-3.3_2002  MT49H16M16FM-4_2002  MT49H16M16FM-5_2002  
MT49H16M16 PDF
Micron
Micron Technology
MT49H16M16FM-5 REDUCED LATENCY DRAM (RLDRAM®)

General Description
The Micron® 256Mb reduced latency DRAM (RLDRAM®) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) form at where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for high bandwidth communication data storage—telecommunications, networking, and cache applications, etc.

Features
• Organization 8 Meg x 32, 16 Meg x 16 in 8 banks
• Cyclic bank addressing for maximum data bandwidth
• Non multiplexed addresses
• Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR
• Up to 600 Mb/sec/pin data rate
• Programmable READ latency (RL) of 5-6
• Data valid signal (DVLD) activated as read data is available
• Data mask signals (DM0/DM1) to mask first and
• second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Pseudo-HSTL 1.8V I/O Supply
• Internal auto precharge
• Refresh requirements: 32ms at 95°C case
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)
• 144-pin, 11mm x 18.5mm µBGA package


other parts : MT49H16M16  MT49H16M16FM-XX  MT49H8M32  MT49H8M32FM-XX  MT49H8M32FM-33  MT49H8M32FM-33IT  MT49H8M32FM-4  MT49H8M32FM-4IT  MT49H8M32FM-5  MT49H8M32FM-5IT  
MT49H16M16FM-5 PDF
Micron
Micron Technology
MT49H16M16BM-5 REDUCED LATENCY DRAM (RLDRAM®)

General Description
The Micron® 256Mb reduced latency DRAM (RLDRAM®) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) form at where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for high bandwidth communication data storage—telecommunications, networking, and cache applications, etc.

Features
• Organization 8 Meg x 32, 16 Meg x 16 in 8 banks
• Cyclic bank addressing for maximum data bandwidth
• Non multiplexed addresses
• Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR
• Up to 600 Mb/sec/pin data rate
• Programmable READ latency (RL) of 5-6
• Data valid signal (DVLD) activated as read data is available
• Data mask signals (DM0/DM1) to mask first and
• second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Pseudo-HSTL 1.8V I/O Supply
• Internal auto precharge
• Refresh requirements: 32ms at 95°C case
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)
• 144-pin, 11mm x 18.5mm µBGA package


other parts : MT49H16M16  MT49H16M16FM-XX  MT49H8M32  MT49H8M32FM-XX  MT49H8M32FM-33  MT49H8M32FM-33IT  MT49H8M32FM-4  MT49H8M32FM-4IT  MT49H8M32FM-5  MT49H8M32FM-5IT  
MT49H16M16BM-5 PDF
Micron
Micron Technology
MT49H16M16BM-4 REDUCED LATENCY DRAM (RLDRAM®)

General Description
The Micron® 256Mb reduced latency DRAM (RLDRAM®) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) form at where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for high bandwidth communication data storage—telecommunications, networking, and cache applications, etc.

Features
• Organization 8 Meg x 32, 16 Meg x 16 in 8 banks
• Cyclic bank addressing for maximum data bandwidth
• Non multiplexed addresses
• Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR
• Up to 600 Mb/sec/pin data rate
• Programmable READ latency (RL) of 5-6
• Data valid signal (DVLD) activated as read data is available
• Data mask signals (DM0/DM1) to mask first and
• second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Pseudo-HSTL 1.8V I/O Supply
• Internal auto precharge
• Refresh requirements: 32ms at 95°C case
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)
• 144-pin, 11mm x 18.5mm µBGA package


other parts : MT49H16M16  MT49H16M16FM-XX  MT49H8M32  MT49H8M32FM-XX  MT49H8M32FM-33  MT49H8M32FM-33IT  MT49H8M32FM-4  MT49H8M32FM-4IT  MT49H8M32FM-5  MT49H8M32FM-5IT  
MT49H16M16BM-4 PDF
Micron
Micron Technology
MT49H16M16FM-4_2002 REDUCED LATENCY DRAM (RLDRAM®)

GENERAL DESCRIPTION
The Micron® 256Mb Reduced Latency DRAM (RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for communication data storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache applications requiring large amounts of memory.

FEATURES
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Cyclic bank addressing for maximum data out bandwidth
• Non-multiplexed addresses
• Non-interruptible sequential burst of two (2-bit
   prefetch) and four (4-bit prefetch) DDR
• Target 600 Mb/s/p data rate
• Programmable Read Latency (RL) of 5-8
• Data valid signal (DVLD) activated as read data is available
• Data Mask signals (DM0/DM1) to mask first and
   second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• Pseudo-HSTL 1.8V I/O Supply
• Internal Auto Precharge
• Refresh requirements: 32ms at 100°C junction
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)


other parts : MT49H16M16_2002  MT49H16M16FM-XX_2002  MT49H8M32_2002  MT49H8M32FM-XX_2002  MT49H8M32FM-3.3_2002  MT49H8M32FM-4_2002  MT49H8M32FM-5_2002  MT49H16M16FM-3.3_2002  MT49H16M16FM-5_2002  
MT49H16M16FM-4 PDF
Micron
Micron Technology
MT49H16M16FM-5_2002 REDUCED LATENCY DRAM (RLDRAM®)

GENERAL DESCRIPTION
The Micron® 256Mb Reduced Latency DRAM (RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for communication data storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache applications requiring large amounts of memory.

FEATURES
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Cyclic bank addressing for maximum data out bandwidth
• Non-multiplexed addresses
• Non-interruptible sequential burst of two (2-bit
   prefetch) and four (4-bit prefetch) DDR
• Target 600 Mb/s/p data rate
• Programmable Read Latency (RL) of 5-8
• Data valid signal (DVLD) activated as read data is available
• Data Mask signals (DM0/DM1) to mask first and
   second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• Pseudo-HSTL 1.8V I/O Supply
• Internal Auto Precharge
• Refresh requirements: 32ms at 100°C junction
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)


other parts : MT49H16M16_2002  MT49H16M16FM-XX_2002  MT49H8M32_2002  MT49H8M32FM-XX_2002  MT49H8M32FM-3.3_2002  MT49H8M32FM-4_2002  MT49H8M32FM-5_2002  MT49H16M16FM-3.3_2002  MT49H16M16FM-4_2002  
MT49H16M16FM-5 PDF
Micron
Micron Technology
MT49H16M16FM-4 REDUCED LATENCY DRAM (RLDRAM®)

General Description
The Micron® 256Mb reduced latency DRAM (RLDRAM®) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) form at where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for high bandwidth communication data storage—telecommunications, networking, and cache applications, etc.

Features
• Organization 8 Meg x 32, 16 Meg x 16 in 8 banks
• Cyclic bank addressing for maximum data bandwidth
• Non multiplexed addresses
• Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR
• Up to 600 Mb/sec/pin data rate
• Programmable READ latency (RL) of 5-6
• Data valid signal (DVLD) activated as read data is available
• Data mask signals (DM0/DM1) to mask first and
• second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Pseudo-HSTL 1.8V I/O Supply
• Internal auto precharge
• Refresh requirements: 32ms at 95°C case
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)
• 144-pin, 11mm x 18.5mm µBGA package


other parts : MT49H16M16  MT49H16M16FM-XX  MT49H8M32  MT49H8M32FM-XX  MT49H8M32FM-33  MT49H8M32FM-33IT  MT49H8M32FM-4  MT49H8M32FM-4IT  MT49H8M32FM-5  MT49H8M32FM-5IT  
MT49H16M16FM-4 PDF
Micron
Micron Technology
MT49H16M16FM-XX_2002 REDUCED LATENCY DRAM (RLDRAM®)

GENERAL DESCRIPTION
The Micron® 256Mb Reduced Latency DRAM (RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for communication data storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache applications requiring large amounts of memory.

FEATURES
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Cyclic bank addressing for maximum data out bandwidth
• Non-multiplexed addresses
• Non-interruptible sequential burst of two (2-bit
   prefetch) and four (4-bit prefetch) DDR
• Target 600 Mb/s/p data rate
• Programmable Read Latency (RL) of 5-8
• Data valid signal (DVLD) activated as read data is available
• Data Mask signals (DM0/DM1) to mask first and
   second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• Pseudo-HSTL 1.8V I/O Supply
• Internal Auto Precharge
• Refresh requirements: 32ms at 100°C junction
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)


other parts : MT49H16M16_2002  MT49H8M32_2002  MT49H8M32FM-XX_2002  MT49H8M32FM-3.3_2002  MT49H8M32FM-4_2002  MT49H8M32FM-5_2002  MT49H16M16FM-3.3_2002  MT49H16M16FM-4_2002  MT49H16M16FM-5_2002  
MT49H16M16FM-XX PDF
Micron
Micron Technology
MT49H16M16BM-33 REDUCED LATENCY DRAM (RLDRAM®)

General Description
The Micron® 256Mb reduced latency DRAM (RLDRAM®) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) form at where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for high bandwidth communication data storage—telecommunications, networking, and cache applications, etc.

Features
• Organization 8 Meg x 32, 16 Meg x 16 in 8 banks
• Cyclic bank addressing for maximum data bandwidth
• Non multiplexed addresses
• Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR
• Up to 600 Mb/sec/pin data rate
• Programmable READ latency (RL) of 5-6
• Data valid signal (DVLD) activated as read data is available
• Data mask signals (DM0/DM1) to mask first and
• second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Pseudo-HSTL 1.8V I/O Supply
• Internal auto precharge
• Refresh requirements: 32ms at 95°C case
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)
• 144-pin, 11mm x 18.5mm µBGA package


other parts : MT49H16M16  MT49H16M16FM-XX  MT49H8M32  MT49H8M32FM-XX  MT49H8M32FM-33  MT49H8M32FM-33IT  MT49H8M32FM-4  MT49H8M32FM-4IT  MT49H8M32FM-5  MT49H8M32FM-5IT  
MT49H16M16BM-33 PDF
Micron
Micron Technology
MT49H16M16FM-XX REDUCED LATENCY DRAM (RLDRAM®)

General Description
The Micron® 256Mb reduced latency DRAM (RLDRAM®) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) form at where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for high bandwidth communication data storage—telecommunications, networking, and cache applications, etc.

Features
• Organization 8 Meg x 32, 16 Meg x 16 in 8 banks
• Cyclic bank addressing for maximum data bandwidth
• Non multiplexed addresses
• Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR
• Up to 600 Mb/sec/pin data rate
• Programmable READ latency (RL) of 5-6
• Data valid signal (DVLD) activated as read data is available
• Data mask signals (DM0/DM1) to mask first and
• second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Pseudo-HSTL 1.8V I/O Supply
• Internal auto precharge
• Refresh requirements: 32ms at 95°C case
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)
• 144-pin, 11mm x 18.5mm µBGA package


other parts : MT49H16M16  MT49H8M32  MT49H8M32FM-XX  MT49H8M32FM-33  MT49H8M32FM-33IT  MT49H8M32FM-4  MT49H8M32FM-4IT  MT49H8M32FM-5  MT49H8M32FM-5IT  MT49H8M32BM-33  
MT49H16M16FM-XX PDF
Micron
Micron Technology
MT49H16M16FM-33 REDUCED LATENCY DRAM (RLDRAM®)

General Description
The Micron® 256Mb reduced latency DRAM (RLDRAM®) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) form at where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for high bandwidth communication data storage—telecommunications, networking, and cache applications, etc.

Features
• Organization 8 Meg x 32, 16 Meg x 16 in 8 banks
• Cyclic bank addressing for maximum data bandwidth
• Non multiplexed addresses
• Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR
• Up to 600 Mb/sec/pin data rate
• Programmable READ latency (RL) of 5-6
• Data valid signal (DVLD) activated as read data is available
• Data mask signals (DM0/DM1) to mask first and
• second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Pseudo-HSTL 1.8V I/O Supply
• Internal auto precharge
• Refresh requirements: 32ms at 95°C case
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)
• 144-pin, 11mm x 18.5mm µBGA package


other parts : MT49H16M16  MT49H16M16FM-XX  MT49H8M32  MT49H8M32FM-XX  MT49H8M32FM-33  MT49H8M32FM-33IT  MT49H8M32FM-4  MT49H8M32FM-4IT  MT49H8M32FM-5  MT49H8M32FM-5IT  
MT49H16M16FM-33 PDF

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