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MC74AC109D

  

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ON-Semiconductor
ON Semiconductor
MC74AC109D Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109  74ACT109  MC74AC109  MC74AC109DR2  MC74AC109DT  MC74AC109DTR2  MC74AC109M  MC74AC109MEL  MC74AC109N  MC74ACT109  
MC74AC109D PDF
Motorola
Motorola => Freescale
MC74AC109D Dual JK positive edge-triggered flip-flop

The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous


other parts : 74AC109  74ACT109  MC74AC109  MC74AC109N  MC74ACT109  MC74ACT109D  MC74ACT109N  
MC74AC109D PDF
ON-Semiconductor
ON Semiconductor
MC74AC109D_2001 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109_2001  74ACT109_2001  MC74AC109_2001  MC74ACT109_2001  MC74AC109N_2001  MC74AC109DR2_2001  MC74AC109DT_2001  MC74AC109DTR2_2001  MC74ACT109N_2001  MC74ACT109D_2001  
MC74AC109D PDF
ONSEMI
ON Semiconductor
MC74AC109D Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109  74ACT109  MC74AC109  MC74ACT109  MC74AC109N  MC74AC109DR2  MC74AC109DT  MC74AC109DTR2  MC74ACT109N  MC74ACT109D  
MC74AC109D PDF
ON-Semiconductor
ON Semiconductor
MC74AC109DT_2001 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109_2001  74ACT109_2001  MC74AC109_2001  MC74ACT109_2001  MC74AC109N_2001  MC74AC109D_2001  MC74AC109DR2_2001  MC74AC109DTR2_2001  MC74ACT109N_2001  MC74ACT109D_2001  
MC74AC109DT PDF
ONSEMI
ON Semiconductor
MC74AC109DT Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109  74ACT109  MC74AC109  MC74ACT109  MC74AC109N  MC74AC109D  MC74AC109DR2  MC74AC109DTR2  MC74ACT109N  MC74ACT109D  
MC74AC109DT PDF
ON-Semiconductor
ON Semiconductor
MC74AC109DT Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109  74ACT109  MC74AC109  MC74AC109D  MC74AC109DR2  MC74AC109DTR2  MC74AC109M  MC74AC109MEL  MC74AC109N  MC74ACT109  
MC74AC109DT PDF
ON-Semiconductor
ON Semiconductor
MC74AC109DR2 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109  74ACT109  MC74AC109  MC74AC109D  MC74AC109DT  MC74AC109DTR2  MC74AC109M  MC74AC109MEL  MC74AC109N  MC74ACT109  
MC74AC109DR2 PDF
ON-Semiconductor
ON Semiconductor
MC74AC109DR2_2001 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109_2001  74ACT109_2001  MC74AC109_2001  MC74ACT109_2001  MC74AC109N_2001  MC74AC109D_2001  MC74AC109DT_2001  MC74AC109DTR2_2001  MC74ACT109N_2001  MC74ACT109D_2001  
MC74AC109DR2 PDF
ONSEMI
ON Semiconductor
MC74AC109DR2 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109  74ACT109  MC74AC109  MC74ACT109  MC74AC109N  MC74AC109D  MC74AC109DT  MC74AC109DTR2  MC74ACT109N  MC74ACT109D  
MC74AC109DR2 PDF
ON-Semiconductor
ON Semiconductor
MC74AC109DTR2_2001 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109_2001  74ACT109_2001  MC74AC109_2001  MC74ACT109_2001  MC74AC109N_2001  MC74AC109D_2001  MC74AC109DR2_2001  MC74AC109DT_2001  MC74ACT109N_2001  MC74ACT109D_2001  
MC74AC109DTR2 PDF
ONSEMI
ON Semiconductor
MC74AC109DTR2 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109  74ACT109  MC74AC109  MC74ACT109  MC74AC109N  MC74AC109D  MC74AC109DR2  MC74AC109DT  MC74ACT109N  MC74ACT109D  
MC74AC109DTR2 PDF

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