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M74HC165

  

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ST-Microelectronics
STMicroelectronics
M74HC165 8-bit PISO shift register

Description
The M74HC165 is a high speed CMOS 8-bit PISO (parallel-in-serial-out) shift register fabricated with silicon gate C2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. The parallel data enter when the shift/load input is low and can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock inputs perform identically: one can be used as a clock inhibit by applying a high signal, to allow this operation clocking is accomplished through a 2-input nor gate. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal causes the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

Features
■ High speed:
   – tPD = 15 ns (typ.) at VCC = 6 V
■ Low power dissipation:
   – ICC = 4 μA (max.) at TA = 25 °C
■ High noise immunity:
   VNIH = VNIL = 28 % VCC (Min.)
■ Symmetrical output impedance:
   |IOH| = IOL = 4 mA (min)
■ Balanced propagation delays: tPLH ≅ tPHL
■ Wide operating voltage range:
   VCC (opr) = 2 V to 6 V
■ Pin and function compatible with 74 series 165


other parts : M74HC165B1R  M74HC165RM13TR  M74HC165TTR  
M74HC165 PDF
ST-Microelectronics
STMicroelectronics
M74HC165M1R 8 BIT PISO SHIFT REGISTER

DESCRIPTION
The M74HC165 is an high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated with silicon gate C2MOS technology.
This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry. Parallel data enters when the shift/load input is low. The parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate.
To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal will cause the same response as rising clock edge.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.

■ HIGH SPEED :
   tPD = 15ns (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION:
   ICC =4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28 % VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 4mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ WIDE OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 165


other parts : M74HC165B1R_01  M74HC165RM13TR_01  M74HC165TTR_01  M74HC165_01  
M74HC165M1R PDF
ST-Microelectronics
STMicroelectronics
M74HC165B1R 8-bit PISO shift register

Description
The M74HC165 is a high speed CMOS 8-bit PISO (parallel-in-serial-out) shift register fabricated with silicon gate C2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. The parallel data enter when the shift/load input is low and can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock inputs perform identically: one can be used as a clock inhibit by applying a high signal, to allow this operation clocking is accomplished through a 2-input nor gate. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal causes the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

Features
■ High speed:
   – tPD = 15 ns (typ.) at VCC = 6 V
■ Low power dissipation:
   – ICC = 4 μA (max.) at TA = 25 °C
■ High noise immunity:
   VNIH = VNIL = 28 % VCC (Min.)
■ Symmetrical output impedance:
   |IOH| = IOL = 4 mA (min)
■ Balanced propagation delays: tPLH ≅ tPHL
■ Wide operating voltage range:
   VCC (opr) = 2 V to 6 V
■ Pin and function compatible with 74 series 165


other parts : M74HC165  M74HC165RM13TR  M74HC165TTR  
M74HC165B1R PDF
ST-Microelectronics
STMicroelectronics
M74HC165_01 8 BIT PISO SHIFT REGISTER

DESCRIPTION
The M74HC165 is an high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated with silicon gate C2MOS technology.
This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry. Parallel data enters when the shift/load input is low. The parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate.
To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal will cause the same response as rising clock edge.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.

■ HIGH SPEED :
   tPD = 15ns (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION:
   ICC =4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28 % VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 4mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ WIDE OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 165


other parts : M74HC165M1R  M74HC165B1R_01  M74HC165RM13TR_01  M74HC165TTR_01  
M74HC165_01 PDF
ST-Microelectronics
STMicroelectronics
M74HC165TTR 8-bit PISO shift register

Description
The M74HC165 is a high speed CMOS 8-bit PISO (parallel-in-serial-out) shift register fabricated with silicon gate C2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. The parallel data enter when the shift/load input is low and can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock inputs perform identically: one can be used as a clock inhibit by applying a high signal, to allow this operation clocking is accomplished through a 2-input nor gate. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal causes the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

Features
■ High speed:
   – tPD = 15 ns (typ.) at VCC = 6 V
■ Low power dissipation:
   – ICC = 4 μA (max.) at TA = 25 °C
■ High noise immunity:
   VNIH = VNIL = 28 % VCC (Min.)
■ Symmetrical output impedance:
   |IOH| = IOL = 4 mA (min)
■ Balanced propagation delays: tPLH ≅ tPHL
■ Wide operating voltage range:
   VCC (opr) = 2 V to 6 V
■ Pin and function compatible with 74 series 165


other parts : M74HC165  M74HC165B1R  M74HC165RM13TR  
M74HC165TTR PDF
ST-Microelectronics
STMicroelectronics
M74HC165RM13TR 8-bit PISO shift register

Description
The M74HC165 is a high speed CMOS 8-bit PISO (parallel-in-serial-out) shift register fabricated with silicon gate C2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. The parallel data enter when the shift/load input is low and can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock inputs perform identically: one can be used as a clock inhibit by applying a high signal, to allow this operation clocking is accomplished through a 2-input nor gate. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal causes the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

Features
■ High speed:
   – tPD = 15 ns (typ.) at VCC = 6 V
■ Low power dissipation:
   – ICC = 4 μA (max.) at TA = 25 °C
■ High noise immunity:
   VNIH = VNIL = 28 % VCC (Min.)
■ Symmetrical output impedance:
   |IOH| = IOL = 4 mA (min)
■ Balanced propagation delays: tPLH ≅ tPHL
■ Wide operating voltage range:
   VCC (opr) = 2 V to 6 V
■ Pin and function compatible with 74 series 165


other parts : M74HC165  M74HC165B1R  M74HC165TTR  
M74HC165RM13TR PDF
ST-Microelectronics
STMicroelectronics
M74HC165B1R_01 8 BIT PISO SHIFT REGISTER

DESCRIPTION
The M74HC165 is an high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated with silicon gate C2MOS technology.
This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry. Parallel data enters when the shift/load input is low. The parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate.
To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal will cause the same response as rising clock edge.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.

■ HIGH SPEED :
   tPD = 15ns (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION:
   ICC =4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28 % VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 4mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ WIDE OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 165


other parts : M74HC165M1R  M74HC165RM13TR_01  M74HC165TTR_01  M74HC165_01  
M74HC165B1R_01 PDF
ST-Microelectronics
STMicroelectronics
M74HC165TTR_01 8 BIT PISO SHIFT REGISTER

DESCRIPTION
The M74HC165 is an high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated with silicon gate C2MOS technology.
This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry. Parallel data enters when the shift/load input is low. The parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate.
To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal will cause the same response as rising clock edge.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.

■ HIGH SPEED :
   tPD = 15ns (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION:
   ICC =4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28 % VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 4mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ WIDE OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 165


other parts : M74HC165M1R  M74HC165B1R_01  M74HC165RM13TR_01  M74HC165_01  
M74HC165TTR_01 PDF
ST-Microelectronics
STMicroelectronics
M74HC165RM13TR_01 8 BIT PISO SHIFT REGISTER

DESCRIPTION
The M74HC165 is an high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated with silicon gate C2MOS technology.
This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry. Parallel data enters when the shift/load input is low. The parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate.
To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal will cause the same response as rising clock edge.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.

■ HIGH SPEED :
   tPD = 15ns (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION:
   ICC =4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28 % VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 4mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ WIDE OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 165


other parts : M74HC165M1R  M74HC165B1R_01  M74HC165TTR_01  M74HC165_01  
M74HC165RM13TR_01 PDF

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