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DM74ALS165MX

  

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Fairchild
Fairchild Semiconductor
DM74ALS165MX_2007 8-Bit Parallel In/Serial Out Shift Register

General Description
The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The DM74ALS165 also features a clock inhibit function and a complemented serial output, QH.
Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a LOW CLK input and a LOW-to-HIGH transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. The parallel inputs to the register are enabled while SH/LD is LOW independently of the levels of CLK, CLK INH, or SER inputs.

Features
■ Complementary outputs
■ Direct overriding load (data) inputs
■ Gated clock inputs
■ Parallel-to-serial data conversion


other parts : DM74ALS165_2007  DM74ALS165M_2007  
DM74ALS165MX PDF
Fairchild
Fairchild Semiconductor
DM74ALS165MX 8-Bit Parallel In/Serial Out Shift Register

General Description
The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The DM74ALS165 also features a clock inhibit function and a complemented serial output, QH.
Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a LOW CLK input and a LOW-to-HIGH transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. The parallel inputs to the register are enabled while SH/LD is LOW independently of the levels of CLK, CLK INH, or SER inputs.

Features
■ Complementary outputs
■ Direct overriding load (data) inputs
■ Gated clock inputs
■ Parallel-to-serial data conversion


other parts : DM74ALS165  DM74ALS165M  DM74ALS165N  
DM74ALS165MX PDF

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