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74VHCT20A

  

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ST-Microelectronics
STMicroelectronics
74VHCT20A DUAL 4-INPUT NAND GATE

DESCRIPTION
The 74VHCT20A is an advanced high-speed CMOS DUAL 4-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provides high noise immunity and stable output.

■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX)
■ POWER DOWN


other parts : 74VHCT20AM  74VHCT20AMTR  74VHCT20ATTR  
74VHCT20A PDF
ST-Microelectronics
STMicroelectronics
74VHCT20AM DUAL 4-INPUT NAND GATE

DESCRIPTION
The 74VHCT20A is an advanced high-speed CMOS DUAL 4-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provides high noise immunity and stable output.

■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX)
■ POWER DOWN


other parts : 74VHCT20A  74VHCT20AMTR  74VHCT20ATTR  
74VHCT20AM PDF
ST-Microelectronics
STMicroelectronics
74VHCT20AMTR DUAL 4-INPUT NAND GATE

DESCRIPTION
The 74VHCT20A is an advanced high-speed CMOS DUAL 4-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provides high noise immunity and stable output.

■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX)
■ POWER DOWN


other parts : 74VHCT20A  74VHCT20AM  74VHCT20ATTR  
74VHCT20AMTR PDF
ST-Microelectronics
STMicroelectronics
74VHCT20ATTR DUAL 4-INPUT NAND GATE

DESCRIPTION
The 74VHCT20A is an advanced high-speed CMOS DUAL 4-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provides high noise immunity and stable output.

■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX)
■ POWER DOWN


other parts : 74VHCT20A  74VHCT20AM  74VHCT20AMTR  
74VHCT20ATTR PDF

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