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74LVTH16835MEA

  

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Fairchild
Fairchild Semiconductor
74LVTH16835MEA Low Voltage 18-Bit Universal Bus Driver with Bushold and 3-STATE Outputs

General Description
The LVTH16835 consists of 18-bit universal bus drivers which combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. Data flow from A to Y is controlled by the output-enable (OE) input. This device operates in the transparent mode when the latch-enable (LE) input is HIGH. The A data is latched if the clock (CLK) input is held at a HIGH or LOW logic level. If LE is LOW, the A-bus data is stored in the latch/flip-flop on


other parts : 74LVTH16835MEAX  74LVTH16835MTD  74LVTH16835MTDX  74LVTH16835  
74LVTH16835MEA PDF
Fairchild
Fairchild Semiconductor
74LVTH16835MEA_2000 Low Voltage 18-Bit Universal Bus Driver with Bushold and 3-STATE Outputs

General Description
The LVTH16835 consists of 18-bit universal bus drivers which combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. Data flow from A to Y is controlled by the output-enable (OE) input. This device operates in the transparent mode when the latch-enable (LE) input is HIGH. The A data is latched if the clock (CLK) input is held at a HIGH or LOW logic level. If LE is LOW, the A-bus data is stored in the latch/flip-flop on


other parts : 74LVTH16835_2000  74LVTH16835MEAX_2000  74LVTH16835MTD_2000  74LVTH16835MTDX_2000  
74LVTH16835MEA PDF
Fairchild
Fairchild Semiconductor
74LVTH16835MEAX Low Voltage 18-Bit Universal Bus Driver with Bushold and 3-STATE Outputs

General Description
The LVTH16835 consists of 18-bit universal bus drivers which combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. Data flow from A to Y is controlled by the output-enable (OE) input. This device operates in the transparent mode when the latch-enable (LE) input is HIGH. The A data is latched if the clock (CLK) input is held at a HIGH or LOW logic level. If LE is LOW, the A-bus data is stored in the latch/flip-flop on


other parts : 74LVTH16835MEA  74LVTH16835MTD  74LVTH16835MTDX  74LVTH16835  
74LVTH16835MEAX PDF
Fairchild
Fairchild Semiconductor
74LVTH16835MEAX_2000 Low Voltage 18-Bit Universal Bus Driver with Bushold and 3-STATE Outputs

General Description
The LVTH16835 consists of 18-bit universal bus drivers which combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. Data flow from A to Y is controlled by the output-enable (OE) input. This device operates in the transparent mode when the latch-enable (LE) input is HIGH. The A data is latched if the clock (CLK) input is held at a HIGH or LOW logic level. If LE is LOW, the A-bus data is stored in the latch/flip-flop on


other parts : 74LVTH16835_2000  74LVTH16835MEA_2000  74LVTH16835MTD_2000  74LVTH16835MTDX_2000  
74LVTH16835MEAX PDF

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