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74LVQ573

  

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Fairchild
Fairchild Semiconductor
74LVQ573_1998 Low Voltage Octal Latch with 3-STATE Outputs

General Description
The LVQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The LVQ573 is functionally identical to the LVQ373 but with inputs and outputs on opposite sides of the package.

Features
■ Ideal for low power/low noise 3.3V applications
■ Implements patented EMI reduction circuitry
■ Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages
■ Guaranteed simultaneous switching noise level
   and dynamic threshold performance
■ Improved latch-up immunity
■ Guaranteed incident wave switching into 75Ω
■ 4 kV minimum ESD immunity


other parts : 74LVQ573SC_1998  74LVQ573SJ_1998  74LVQ573QSC_1998  74LVQ573SCX_1998  74LVQ573SJX_1998  74LVQ573QSCX_1998  
74LVQ573 PDF
Fairchild
Fairchild Semiconductor
74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs

General Description
The LVQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The LVQ573 is functionally identical to the LVQ373 but with inputs and outputs on opposite sides of the package.

Features
■ Ideal for low power/low noise 3.3V applications
■ Implements patented EMI reduction circuitry
■ Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages
■ Guaranteed simultaneous switching noise level
   and dynamic threshold performance
■ Improved latch-up immunity
■ Guaranteed incident wave switching into 75Ω
■ 4 kV minimum ESD immunity


other parts : 74LVQ573SC  74LVQ573SJ  74LVQ573QSC  74LVQ573SCX  74LVQ573SJX  74LVQ573QSCX  
74LVQ573 PDF
ST-Microelectronics
STMicroelectronics
74LVQ573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING

DESCRIPTION
The LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V
■ COMPATIBLEWITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC =4 µA (MAX.) at TA = 25 °C
■ LOW NOISE:
   VOLP = 0.5 V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSIONLINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24 mA (MIN)
■ PCI BUS LEVELSGUARANTEED AT 24mA
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 2V to 3.6V (1.2VData Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74LVQ573M  74LVQ573T  
74LVQ573 PDF
ST-Microelectronics
STMicroelectronics
74LVQ573T OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING

DESCRIPTION
The LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V
■ COMPATIBLEWITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC =4 µA (MAX.) at TA = 25 °C
■ LOW NOISE:
   VOLP = 0.5 V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSIONLINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24 mA (MIN)
■ PCI BUS LEVELSGUARANTEED AT 24mA
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 2V to 3.6V (1.2VData Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74LVQ573  74LVQ573M  
74LVQ573T PDF
ST-Microelectronics
STMicroelectronics
74LVQ573M OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING

DESCRIPTION
The LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V
■ COMPATIBLEWITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC =4 µA (MAX.) at TA = 25 °C
■ LOW NOISE:
   VOLP = 0.5 V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSIONLINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24 mA (MIN)
■ PCI BUS LEVELSGUARANTEED AT 24mA
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 2V to 3.6V (1.2VData Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74LVQ573  74LVQ573T  
74LVQ573M PDF
Fairchild
Fairchild Semiconductor
74LVQ573SJ_1998 Low Voltage Octal Latch with 3-STATE Outputs

General Description
The LVQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The LVQ573 is functionally identical to the LVQ373 but with inputs and outputs on opposite sides of the package.

Features
■ Ideal for low power/low noise 3.3V applications
■ Implements patented EMI reduction circuitry
■ Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages
■ Guaranteed simultaneous switching noise level
   and dynamic threshold performance
■ Improved latch-up immunity
■ Guaranteed incident wave switching into 75Ω
■ 4 kV minimum ESD immunity


other parts : 74LVQ573_1998  74LVQ573SC_1998  74LVQ573QSC_1998  74LVQ573SCX_1998  74LVQ573SJX_1998  74LVQ573QSCX_1998  
74LVQ573SJ PDF
Fairchild
Fairchild Semiconductor
74LVQ573SC_1998 Low Voltage Octal Latch with 3-STATE Outputs

General Description
The LVQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The LVQ573 is functionally identical to the LVQ373 but with inputs and outputs on opposite sides of the package.

Features
■ Ideal for low power/low noise 3.3V applications
■ Implements patented EMI reduction circuitry
■ Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages
■ Guaranteed simultaneous switching noise level
   and dynamic threshold performance
■ Improved latch-up immunity
■ Guaranteed incident wave switching into 75Ω
■ 4 kV minimum ESD immunity


other parts : 74LVQ573_1998  74LVQ573SJ_1998  74LVQ573QSC_1998  74LVQ573SCX_1998  74LVQ573SJX_1998  74LVQ573QSCX_1998  
74LVQ573SC PDF
Fairchild
Fairchild Semiconductor
74LVQ573SJ Low Voltage Octal Latch with 3-STATE Outputs

General Description
The LVQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The LVQ573 is functionally identical to the LVQ373 but with inputs and outputs on opposite sides of the package.

Features
■ Ideal for low power/low noise 3.3V applications
■ Implements patented EMI reduction circuitry
■ Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages
■ Guaranteed simultaneous switching noise level
   and dynamic threshold performance
■ Improved latch-up immunity
■ Guaranteed incident wave switching into 75Ω
■ 4 kV minimum ESD immunity


other parts : 74LVQ573  74LVQ573SC  74LVQ573QSC  74LVQ573SCX  74LVQ573SJX  74LVQ573QSCX  
74LVQ573SJ PDF
Fairchild
Fairchild Semiconductor
74LVQ573SC Low Voltage Octal Latch with 3-STATE Outputs

General Description
The LVQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The LVQ573 is functionally identical to the LVQ373 but with inputs and outputs on opposite sides of the package.

Features
■ Ideal for low power/low noise 3.3V applications
■ Implements patented EMI reduction circuitry
■ Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages
■ Guaranteed simultaneous switching noise level
   and dynamic threshold performance
■ Improved latch-up immunity
■ Guaranteed incident wave switching into 75Ω
■ 4 kV minimum ESD immunity


other parts : 74LVQ573  74LVQ573SJ  74LVQ573QSC  74LVQ573SCX  74LVQ573SJX  74LVQ573QSCX  
74LVQ573SC PDF
Fairchild
Fairchild Semiconductor
74LVQ573SJX_1998 Low Voltage Octal Latch with 3-STATE Outputs

General Description
The LVQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The LVQ573 is functionally identical to the LVQ373 but with inputs and outputs on opposite sides of the package.

Features
■ Ideal for low power/low noise 3.3V applications
■ Implements patented EMI reduction circuitry
■ Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages
■ Guaranteed simultaneous switching noise level
   and dynamic threshold performance
■ Improved latch-up immunity
■ Guaranteed incident wave switching into 75Ω
■ 4 kV minimum ESD immunity


other parts : 74LVQ573_1998  74LVQ573SC_1998  74LVQ573SJ_1998  74LVQ573QSC_1998  74LVQ573SCX_1998  74LVQ573QSCX_1998  
74LVQ573SJX PDF
Fairchild
Fairchild Semiconductor
74LVQ573QSC Low Voltage Octal Latch with 3-STATE Outputs

General Description
The LVQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The LVQ573 is functionally identical to the LVQ373 but with inputs and outputs on opposite sides of the package.

Features
■ Ideal for low power/low noise 3.3V applications
■ Implements patented EMI reduction circuitry
■ Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages
■ Guaranteed simultaneous switching noise level
   and dynamic threshold performance
■ Improved latch-up immunity
■ Guaranteed incident wave switching into 75Ω
■ 4 kV minimum ESD immunity


other parts : 74LVQ573  74LVQ573SC  74LVQ573SJ  74LVQ573SCX  74LVQ573SJX  74LVQ573QSCX  
74LVQ573QSC PDF
ST-Microelectronics
STMicroelectronics
74LVQ573_01 LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING

DESCRIPTION
The 74LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   tPD = 5.8 ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA=25°C
■ LOW NOISE:
   VOLP = 0.5V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74LVQ573M_01  74LVQ573MTR  74LVQ573TTR  
74LVQ573_01 PDF

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