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74ACT109

  

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Fairchild
Fairchild Semiconductor
74ACT109 Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109CW  
74ACT109 PDF
Motorola
Motorola => Freescale
74ACT109 Dual JK positive edge-triggered flip-flop

The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous


other parts : 74AC109  MC74AC109  MC74AC109D  MC74AC109N  MC74ACT109  MC74ACT109D  MC74ACT109N  
74ACT109 PDF
ON-Semiconductor
ON Semiconductor
74ACT109 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109  MC74AC109  MC74AC109D  MC74AC109DR2  MC74AC109DT  MC74AC109DTR2  MC74AC109M  MC74AC109MEL  MC74AC109N  MC74ACT109  
74ACT109 PDF
ONSEMI
ON Semiconductor
74ACT109 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109  MC74AC109  MC74ACT109  MC74AC109N  MC74AC109D  MC74AC109DR2  MC74AC109DT  MC74AC109DTR2  MC74ACT109N  MC74ACT109D  
74ACT109 PDF
ON-Semiconductor
ON Semiconductor
74ACT109_2001 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74AC109_2001  MC74AC109_2001  MC74ACT109_2001  MC74AC109N_2001  MC74AC109D_2001  MC74AC109DR2_2001  MC74AC109DT_2001  MC74AC109DTR2_2001  MC74ACT109N_2001  MC74ACT109D_2001  
74ACT109 PDF
TI
Texas Instruments
74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

description/ordering information
The ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not


other parts : 54ACT109  CD54ACT109  CD54ACT109F3A  CD74ACT109  CD74ACT109E  CD74ACT109EE4  CD74ACT109M  CD74ACT109M96  CD74ACT109M96E4  CD74ACT109M96G4  
74ACT109 PDF
Fairchild
Fairchild Semiconductor
74ACT109SC Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  
74ACT109SC PDF
Fairchild
Fairchild Semiconductor
74ACT109PC Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  
74ACT109PC PDF
Fairchild
Fairchild Semiconductor
74ACT109CW Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  
74ACT109CW PDF
Fairchild
Fairchild Semiconductor
74ACT109MTC Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  
74ACT109MTC PDF
Fairchild
Fairchild Semiconductor
74ACT109SCX Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  
74ACT109SCX PDF
Fairchild
Fairchild Semiconductor
74ACT109PCX Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  
74ACT109PCX PDF

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