Manufacturer 
Part no 
Description 
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Motorola => Freescale 
74ACT109

Dual JK positive edgetriggered flipflop
The MC74AC109/74ACT109 consists of two highspeed completely independent transition clocked JK flipflops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flipflop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH • Outputs Source/Sink 24 mA • ′ACT109 Has TTL Compatible Inputs
other parts :
74AC109
MC74AC109
MC74AC109D
MC74AC109N
MC74ACT109
MC74ACT109D
MC74ACT109N


Texas Instruments 
74ACT109

DUAL JK POSITIVEEDGETRIGGERED FLIPFLOPS WITH CLEAR AND PRESET
description/ordering information The ’ACT109 devices contain two independent JK positiveedgetriggered flipflops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setuptime requirements are transferred to the outputs on the positivegoing edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the holdtime interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flipflops can perform as toggle flipflops by grounding K and tying J high. They also can perform as Dtype flipflops if J and K are tied together. ● Inputs Are TTLVoltage Compatible ● Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption ● Balanced Propagation Delays ● ±24mA Output Drive Current – Fanout to 15 F Devices ● SCRLatchupResistant CMOS Process and Circuit Design ● Exceeds 2kV ESD Protection Per MILSTD883, Method 3015
other parts :
54ACT109
CD54ACT109
CD74ACT109
CD74ACT109EE4
CD74ACT109M
CD74ACT109M96
CD74ACT109M96E4
CD74ACT109ME4
CD54ACT109F3A
CD74ACT109E


ON Semiconductor 
74ACT109_2001

Dual JK Positive Edge−Triggered Flip−Flop
The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH • Outputs Source/Sink 24 mA • ′ACT109 Has TTL Compatible Inputs
other parts :
74AC109_2001
MC74AC109_2001
MC74ACT109_2001
MC74AC109N_2001
MC74AC109D_2001
MC74AC109DR2_2001
MC74AC109DT_2001
MC74AC109DTR2_2001
MC74ACT109N_2001
MC74ACT109D_2001


ON Semiconductor 
74ACT109

Dual JK Positive Edge−Triggered Flip−Flop
The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH • Outputs Source/Sink 24 mA • ′ACT109 Has TTL Compatible Inputs
other parts :
74AC109
MC74AC109
MC74ACT109
MC74AC109N
MC74AC109D
MC74AC109DR2
MC74AC109DT
MC74AC109DTR2
MC74ACT109N
MC74ACT109D


ON Semiconductor 
74ACT109

Dual JK Positive Edge−Triggered Flip−Flop
The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH
• Outputs Source/Sink 24 mA • ′ACT109 Has TTL Compatible Inputs
other parts :
74AC109
MC74AC109
MC74AC109D
MC74AC109DR2
MC74AC109DT
MC74AC109DTR2
MC74AC109M
MC74AC109MEL
MC74AC109N
MC74ACT109


Fairchild Semiconductor 
74ACT109

Dual JK Positive EdgeTriggered FlipFlop
General Description The AC/ACT109 consists of two highspeed completely independent transition clocked JK flipflops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a DType flipflop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. Features ■ ICC reduced by 50% ■ Outputs source/sink 24 mA ■ ACT109 has TTLcompatible inputs
other parts :
74AC109
74AC109MTC
74AC109MTCX
74AC109PC
74AC109PCX
74AC109SC
74AC109SCX
74AC109SJ
74AC109SJX
74ACT109CW


Fairchild Semiconductor 
74ACT109PC

Dual JK Positive EdgeTriggered FlipFlop
General Description The AC/ACT109 consists of two highspeed completely independent transition clocked JK flipflops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a DType flipflop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. Features ■ ICC reduced by 50% ■ Outputs source/sink 24 mA ■ ACT109 has TTLcompatible inputs
other parts :
74AC109
74AC109MTC
74AC109MTCX
74AC109PC
74AC109PCX
74AC109SC
74AC109SCX
74AC109SJ
74AC109SJX
74ACT109


Fairchild Semiconductor 
74ACT109CW

Dual JK Positive EdgeTriggered FlipFlop
General Description The AC/ACT109 consists of two highspeed completely independent transition clocked JK flipflops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a DType flipflop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. Features ■ ICC reduced by 50% ■ Outputs source/sink 24 mA ■ ACT109 has TTLcompatible inputs
other parts :
74AC109
74AC109MTC
74AC109MTCX
74AC109PC
74AC109PCX
74AC109SC
74AC109SCX
74AC109SJ
74AC109SJX
74ACT109


Fairchild Semiconductor 
74ACT109SC

Dual JK Positive EdgeTriggered FlipFlop
General Description The AC/ACT109 consists of two highspeed completely independent transition clocked JK flipflops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a DType flipflop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. Features ■ ICC reduced by 50% ■ Outputs source/sink 24 mA ■ ACT109 has TTLcompatible inputs
other parts :
74AC109
74AC109MTC
74AC109MTCX
74AC109PC
74AC109PCX
74AC109SC
74AC109SCX
74AC109SJ
74AC109SJX
74ACT109


Fairchild Semiconductor 
74ACT109MTC

Dual JK Positive EdgeTriggered FlipFlop
General Description The AC/ACT109 consists of two highspeed completely independent transition clocked JK flipflops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a DType flipflop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. Features ■ ICC reduced by 50% ■ Outputs source/sink 24 mA ■ ACT109 has TTLcompatible inputs
other parts :
74AC109
74AC109MTC
74AC109MTCX
74AC109PC
74AC109PCX
74AC109SC
74AC109SCX
74AC109SJ
74AC109SJX
74ACT109


Fairchild Semiconductor 
74ACT109SCX

Dual JK Positive EdgeTriggered FlipFlop
General Description The AC/ACT109 consists of two highspeed completely independent transition clocked JK flipflops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a DType flipflop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. Features ■ ICC reduced by 50% ■ Outputs source/sink 24 mA ■ ACT109 has TTLcompatible inputs
other parts :
74AC109
74AC109MTC
74AC109MTCX
74AC109PC
74AC109PCX
74AC109SC
74AC109SCX
74AC109SJ
74AC109SJX
74ACT109


Fairchild Semiconductor 
74ACT109PCX

Dual JK Positive EdgeTriggered FlipFlop
General Description The AC/ACT109 consists of two highspeed completely independent transition clocked JK flipflops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a DType flipflop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. Features ■ ICC reduced by 50% ■ Outputs source/sink 24 mA ■ ACT109 has TTLcompatible inputs
other parts :
74AC109
74AC109MTC
74AC109MTCX
74AC109PC
74AC109PCX
74AC109SC
74AC109SCX
74AC109SJ
74AC109SJX
74ACT109

