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74AC37397

  

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ON-Semiconductor
ON Semiconductor
74AC373 Octal Transparent Latch with 3-State Outputs

The MC74AC373/74ACT373 consists of eight latches with 3–state outputs for bus organized system applications. The flip–flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

• Eight Latches in a Single Package
• 3–State Outputs for Bus Interfacing
• Outputs Source/Sink 24 mA
• ′ACT373 Has TTL Compatible Inputs


other parts : 74ACT373  MC74AC373  MC74AC373M  MC74ACT373  MC74ACT373M  MC74AC373N_01  MC74ACT373N_01  MC74AC373DW_01  MC74AC373DWR2_01  MC74ACT373DW_01  
74AC373 PDF
Fairchild
Fairchild Semiconductor
74AC373_2005 Octal Transparent Latch with 3-STATE Outputs

General Description
The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

Features
■ ICC and IOZ reduced by 50%
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ ACT373 has TTL-compatible inputs


other parts : 74ACT373_2005  74AC373SC_2005  74AC373SJ_2005  74AC373MTC_2005  74ACT373SC_2005  74ACT373SJ_2005  74ACT373MSA_2005  74ACT373MTC_2005  74AC373SCX_2005  74AC373SJX_2005  
74AC373 PDF
Fairchild
Fairchild Semiconductor
74AC373 Octal Transparent Latch with 3-STATE Outputs

General Description
The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

Features
■ ICC and IOZ reduced by 50%
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ ACT373 has TTL-compatible inputs


other parts : 74AC373MTC  74AC373SC  74AC373SJ  74ACT373  74ACT373MSA  74ACT373MTC  74ACT373SC  74ACT373SJ  74AC373SCX  74AC373SJX  
74AC373 PDF
ST-Microelectronics
STMicroelectronics
74AC373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)

DESCRIPTION
The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level); while OE is in high level the outputs will be in a high impedance state.
This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28 % VCC (MIN.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74AC373B  74AC373M  74AC373MTR  74AC373TTR  
74AC373 PDF
ST-Microelectronics
STMicroelectronics
74AC373B OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)

DESCRIPTION
The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level); while OE is in high level the outputs will be in a high impedance state.
This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28 % VCC (MIN.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74AC373M  74AC373MTR  74AC373TTR  74AC373  
74AC373B PDF
ST-Microelectronics
STMicroelectronics
74AC373M OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)

DESCRIPTION
The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level); while OE is in high level the outputs will be in a high impedance state.
This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28 % VCC (MIN.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74AC373B  74AC373MTR  74AC373TTR  74AC373  
74AC373M PDF
Fairchild
Fairchild Semiconductor
74AC373SC Octal Transparent Latch with 3-STATE Outputs

General Description
The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

Features
■ ICC and IOZ reduced by 50%
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ ACT373 has TTL-compatible inputs


other parts : 74AC373  74AC373MTC  74AC373SJ  74ACT373  74ACT373MSA  74ACT373MTC  74ACT373SC  74ACT373SJ  74AC373SCX  74AC373SJX  
74AC373SC PDF
Fairchild
Fairchild Semiconductor
74AC373PC_2005 Octal Transparent Latch with 3-STATE Outputs

General Description
The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

Features
■ ICC and IOZ reduced by 50%
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ ACT373 has TTL-compatible inputs


other parts : 74AC373_2005  74ACT373_2005  74AC373SC_2005  74AC373SJ_2005  74AC373MTC_2005  74ACT373SC_2005  74ACT373SJ_2005  74ACT373MSA_2005  74ACT373MTC_2005  74AC373SCX_2005  
74AC373PC PDF
Fairchild
Fairchild Semiconductor
74AC373CW Octal Transparent Latch with 3-STATE Outputs

General Description
The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

Features
■ ICC and IOZ reduced by 50%
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ ACT373 has TTL-compatible inputs

74AC373CW PDF
Fairchild
Fairchild Semiconductor
74AC373SJ_2005 Octal Transparent Latch with 3-STATE Outputs

General Description
The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

Features
■ ICC and IOZ reduced by 50%
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ ACT373 has TTL-compatible inputs


other parts : 74AC373_2005  74ACT373_2005  74AC373SC_2005  74AC373MTC_2005  74ACT373SC_2005  74ACT373SJ_2005  74ACT373MSA_2005  74ACT373MTC_2005  74AC373SCX_2005  74AC373SJX_2005  
74AC373SJ PDF
Fairchild
Fairchild Semiconductor
74AC373SC_2005 Octal Transparent Latch with 3-STATE Outputs

General Description
The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

Features
■ ICC and IOZ reduced by 50%
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ ACT373 has TTL-compatible inputs


other parts : 74AC373_2005  74ACT373_2005  74AC373SJ_2005  74AC373MTC_2005  74ACT373SC_2005  74ACT373SJ_2005  74ACT373MSA_2005  74ACT373MTC_2005  74AC373SCX_2005  74AC373SJX_2005  
74AC373SC PDF
Fairchild
Fairchild Semiconductor
74AC373PC Octal Transparent Latch with 3-STATE Outputs

General Description
The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

Features
■ ICC and IOZ reduced by 50%
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ ACT373 has TTL-compatible inputs


other parts : 74AC373  74AC373MTC  74AC373SC  74AC373SJ  74ACT373  74ACT373MSA  74ACT373MTC  74ACT373SC  74ACT373SJ  74AC373SCX  
74AC373PC PDF

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