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74AC109

  

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Motorola
Motorola => Freescale
74AC109 Dual JK positive edge-triggered flip-flop

The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous


other parts : 74ACT109  MC74AC109  MC74AC109D  MC74AC109N  MC74ACT109  MC74ACT109D  MC74ACT109N  
74AC109 PDF
ON-Semiconductor
ON Semiconductor
74AC109_2001 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74ACT109_2001  MC74AC109_2001  MC74ACT109_2001  MC74AC109N_2001  MC74AC109D_2001  MC74AC109DR2_2001  MC74AC109DT_2001  MC74AC109DTR2_2001  MC74ACT109N_2001  MC74ACT109D_2001  
74AC109 PDF
ONSEMI
ON Semiconductor
74AC109 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74ACT109  MC74AC109  MC74ACT109  MC74AC109N  MC74AC109D  MC74AC109DR2  MC74AC109DT  MC74AC109DTR2  MC74ACT109N  MC74ACT109D  
74AC109 PDF
ON-Semiconductor
ON Semiconductor
74AC109 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD


other parts : 74ACT109  MC74AC109  MC74AC109D  MC74AC109DR2  MC74AC109DT  MC74AC109DTR2  MC74AC109M  MC74AC109MEL  MC74AC109N  MC74ACT109  
74AC109 PDF
Fairchild
Fairchild Semiconductor
74AC109 Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  74ACT109CW  
74AC109 PDF
Fairchild
Fairchild Semiconductor
74AC109CW Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  
74AC109CW PDF
Fairchild
Fairchild Semiconductor
74AC109SJ Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJX  74ACT109  74ACT109CW  
74AC109SJ PDF
Fairchild
Fairchild Semiconductor
74AC109SC Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  74ACT109CW  
74AC109SC PDF
Fairchild
Fairchild Semiconductor
74AC109PC Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  74ACT109CW  
74AC109PC PDF
Fairchild
Fairchild Semiconductor
74AC109PCX Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  74ACT109CW  
74AC109PCX PDF
Fairchild
Fairchild Semiconductor
74AC109MTC Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  74ACT109CW  
74AC109MTC PDF
Fairchild
Fairchild Semiconductor
74AC109SJX Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74ACT109  74ACT109CW  
74AC109SJX PDF

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